Flip chip technology provides a good illustration of the application of failure analysis. Although there can be numerous types of fails with their own nuances, they generally involve the die (or chip), the C4s connecting the die to the carrier, the carrier (often a laminate), and the BGAs connecting the carrier to the printed circuit board (not shown here).
“Pick and place” is a common term used in microelectronics manufacturing to refer to the process whereby components such as die are selected from a cue of parts, and positioned on the carrier. If the placement parameters are set too aggressively, the chip may be damaged. Occasionally the damage is severe enough to be visible directly, as shown in the photograph. A more subtle version occurs when the damage is latent, and only appears after the high thermo-mechanical stresses later in the assembly.
Integrity of the metal interfaces forming the connection between the chip and the carrier depends in large part on the metals and the quality of the deposition process. It is well known the micro-voids are subject to migration, particularly at high temperatures. Coalescence of the voids into larger aggregates may be problematic at metal/metal interfaces. The high magnification micrograph shows macroscopic collection of voids along the interface of the C4 pad and solder. In this case, the connection is almost completely broken. This failure mechanism is thermally driven.
One of the most common failure mechanisms arises from thermal cycling. The coefficient of thermal expansion of the die is substantially different than that of the laminate carrier, stressing the C4 connections as the temperature of the part changes. The first micrograph shows severe cracking of the solder at both the chip side and carrier side of the connection. Multiple fractures give the solder a crumbling appearance. The second micrograph shows a continuous crack near the C4 pad of the die. The last two micrographs are SEM images, and show sharp detail of the solder cracks.
Thermal cycling fatigue affects the BGAs as well as the C4s. The micrograph shows a BGA crack that formed during thermal cycle stress.
Under heavy current, electron “bombardment” can deform conductors. Interfaces of C4s are singularly susceptible, depending on the electron flow, a schematic of which is shown in the figure. The micrographs show the failure for both sides of the C4. Note how heavy voiding along the interface line.
When stressed at high temperature, humidity and bias, printed circuits are prone to form short circuits from the imbedded materials. Originally believed to grow from the positive side, these type of failures were called Conductive Anodic Filaments (CAF). The term CAF is still used despite the fact that growth can occur from either polarity. Because printed circuits are constructed from fiber glass reinforced resins, the fibers provide a surface on which the filament grows. A typical CAF is shown in the micrograph.