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Confirmed Presenters at 2012 Electronics Packaging Symposium

Speaker                                Organization                                Speaker   Organization
Alfred Zinn   Lockheed Martin Space System Company ATC   Marc Papageorge   Icintek
Aric Shorey   Corning   Mark Christensen   Prismark Partners
Arun Gowda   GE Global Research   Nathan Gill   BAE
Avram Bar-Cohen   Defense Advanced Projects Agency    Patrick McCluskey   University of Maryland
Bahgat Sammakia   Binghamton University   Paul Franzon   NCSU
Bin Yu   Albany   Paul Marchal   IMEC
Charles Woychik
  Invensas   Pedro Quintero   University of Puerto Rico
David Altman   Raytheon Integrated Defense Systems   Peter Brofman   IBM
Evan Colgan   IBM   Rabindra Das   Endicott Interconnect Technologies, Inc.
Hendrik Hamann   IBM   Raj Jammy   Sematech
HongWen Zhang   Indium Corp.   Rolf Aschenbrenner   Fraunhofer IZM
James Lu   Rensselaer Polytechnic Institute   Sandeep Tonapi   Anveshak Technology and Knowledge Solutions
Jeremy Muldavin   MIT Lincoln Laboratory   Satish Chaparala   Corning Incorporated
Jim Watkins   University of Massachusetts   Sean Garner   Corning Incorporated
Kamal Sikka   IBM   Shekhar Borkar   Intel
Liang-Yu Chen   OAI/NASA GRC   Subhash Shinde   Sandia National Laboratories
Ljubisa Stevanovic   GE Global Research   Urmi Ray   Qualcomm
Luc Frechette   Universite de Sherbrooke   Yong Liu   Fairchild Semiconductor Corp.
        Yogen Utturkar   GE Global Research


Speaker: Alfred Zinn, Lockheed Martin Space System Company ATC, Senior Scientist

NanoCopper Materials Platform for Electronic Packaging and Printed Electronics with 200 °C Processing Temperature

The Advanced Technology Center of the Lockheed Martin Corporation has developed a nanocopper-based material that can be fused to bulk copper around 200 °C taking advantage of the rapidly decreasing fusion temperature with decreasing particle size at the nanoscale. The nanocopper material has the potential to replace tin-based solder to eliminate whisker growth and mechanical reliability concerns encountered with current lead-free solder. Fully optimized, the fused copper is expected to exhibit 10-15x electrical and thermal conductivity improvements over tin-based materials currently in use. The materials platform is enabled by our scalable Cu nanoparticle fabrication process employing a low cost solution-phase chemical reduction approach. A proprietary mixture of surfactants controls particle size and size distribution as well as stabilizing the particles preventing particle growth and oxidation, which would otherwise degrade its activity. We have demonstrated assembly of fully functional LED test boards using a paste formulated with nanocopper that exhibits a consistency very similar to standard tin-based solder paste. To date, we have demonstrated 26-pin through-hole connector assembly and a variety of surface mount components. We demonstrated feasibility of drop-in solder replacement using standard stencil and pick & place packaging equipment as well as demonstrated feasibility of using the material for printed electronics applications.

  Dr. Zinn received his Doctor of Science degree in Chemistry in 1990 from the Philipps University, Marburg, Germany. Following completion of his graduate studies, Dr. Zinn spent five years at UCLA as a lecturer and conducting postdoctoral research on low-temperature CVD for interconnect, diffusion, and migration barrier deposition, as well as magnetic nanomaterials design and synthesis. In 2004, he joined Lockheed Martin Space Systems Company Advanced technology Center in Palo Alto, CA developing high-temperature materials systems, nanostructured functional materials (electrical, thermal, thermoelectric), modeling quantum/superlattice structures and devices, high performance energy conversion devices (solar, high & low quality heat conversion). He holds seven patents in materials, structures and processing, two THz technology patents, with ten additional patents pending (multiple international filings) as well as four trade secrets. He has authored or co-authored over 20 archival journal publications, including book chapters in "The Chemistry of Metal CVD" as well as the "Encyclopedia of Inorganic Chemistry.
Speaker: Aric Shorey, Corning Incorporated, Sr. Technical Manager


Development of Through Glass Via (TGV) Substrates for 3D-IC Integration

Through-substrate vias are critical for 3DS-IC integration. The choice of glass as an interposer substrate, TGV, present some interesting challenges and opportunities, making glass a compelling alternative to silicon. There are two primary challenges to begin building a precision interposer in thin glass. The first is high quality thin glass wafers (300 mm OD, thickness < 0.10 mm, warp and TTV of 30 µm and 1 µm respectively). The second challenge is developing a process capable of providing small precision vias in a cost- effective way. Glass represents a large class of materials with a wide range of material properties. The first step in developing TGV is to identify the most appropriate glass composition for the application, which furthermore defines important properties such as coefficient of thermal expansion (CTE) and other mechanical properties, chemical durability and electrical properties. The manufacturing process used to develop the glass has a significant impact on quality and manufacturability. Fusion formed glass provides a solution for high volume manufacturing supply in an as-formed, ultra-thin, pristine glass manufactured to tight tolerances, and avoids the issues associated with polishing or thinning. The supply of < 100 µm as-formed ultra-thin glass wafers can compare very favorably in cost relative to polished or thinned glass as well as thinned silicon wafer. While there are many technologies that have demonstrated vias in glass, challenges related to via size and pitch, wafer strength and reliability remain to be resolved. However, substantial progress has been made to meet these challenges. Specific characterization data from some of these processes to demonstrate vias on the order of 20 µm diameter with a 100 µm glass thickness will be presented. 

  ShoreyAric is a Sr. Technical Manager at Corning, Incorporated working on the Semiconductor Glass Wafer program. He has BS/MS in Mechanical Engineering and a PhD in Materials Science – all from the University of Rochester. He has spent the majority of his career in material's finishing and characterization for the telecommunications, precision optics and semiconductor industries. 
Speaker: Arun Gowda, GE Global Research

Power Overlay Packaging Platform for High Performance Power Electronics

There has been significant advancement in Integrated Chip (IC) packaging over the last couple of decades and continues with 3D and embedded packaging. In contrast, areas such as power electronics and heterogeneous System-in-Packages (SiPs) have seen notable advancement in their packaging technology only recently. These advancements are driven by the industry segments and semiconductor device trends. For example, recent advancements in the power electronics industry are driven by emerging, high-growth segments like vehicle electrification, energy efficient products, etc. These applications demand high efficiency miniaturized systems which are capable of operating across expanding temperature ranges. The emergence of SiC and GaN power devices and the improvement in existing Si power devices address some of these application needs; however suitable packaging is essential to realize the full entitlement of these devices. Power Overlay (POL) packaging is an example of a disruptive packaging platform that provides high-density, high-efficiency, and reliable device-level interconnects to yield improved module-level electrical, thermal and mechanical functionality. POL has been demonstrated in several areas and levels of implementation, for power devices and modules, Radio Frequency (RF) modules, ASICs and Microprocessors, sensing devices, and embedded electronics. The attributes of GE's POL packaging technology and key performance advantages with respect to power electronics, is discussed in more detail in this presentation.

  ArunArun Gowda leads the Electronics Packaging and Miniaturization group at GE Global Research, responsible for developing advanced packaging and subsystem integration for GE's diverse applications, including Aviation, Healthcare, and Energy. Previous to this role, Arun was a Senior Mechanical Engineer at GE Global Research and led research projects in the area of advanced power packaging and thermal management. Arun graduated from Binghamton University with a M.S and Ph.D. from the System Science and Industrial Engineering Department, specializing in Electronics Packaging, in 2001 and 2004 respectively. He received Outstanding Academic Achievement awards for both his M.S. and Ph.D work. He is also the recipient of the 2002 Charles Hutchins Educational Grant from SMTA and Circuits Assembly Magazine. Arun has over 35 publications and over 30 issued/pending patents applications. Arun is a Six Sigma Black Belt and a TRIZ Level 3 Practitioner. He is also a visiting professor in the System Science and Industrial Engineering Department at Binghamton University. He is a co-organizer of the annual GE-Binghamton University Electronics Packaging Symposium and has chaired tracks and sessions at numerous ASME and IEEE conferences.
Speaker: Avram Bar-Cohen, Defense Advanced Projects Agency

Gen3 Thermal Packaging Technology: Microfluidics and Thermal Interconnects

Throughout the Information Age thermal management technology has played a key role in the continuing miniaturization, performance improvements, and higher reliability of electronic systems. During these 65 years, thermal packaging has evolved from ventilation and air-conditioning to cabinet cooling, to package cooling with heat sinks and cold plates and is currently addressing on-chip hot spots. Despite the aggressive development of advanced heat sinks, TIMs, and spreaders, today's high performance computers and advanced telecommunication systems are severely limited by thermal constraints, due in large part to the inherent limitations of the prevailing "remote cooling" paradigm. To remove a significant barrier to continued Moore's Law progression in electronic components and systems, DARPA is pursuing the aggressive development of Gen3 thermal packaging technology, using microfluidics and thermal interconnects "embedded" in the chip, substrate, and/or package to directly cool the heat generation sites. Following a brief review of the 65 years of thermal packaging technology and the perceived thermal barriers to Moore's Law, attention will turn to the current DARPA Thermal Management Technologies portfolio, with emphasis on the goals and status of these efforts and their impact on the current State-of-the-Art in electronic cooling. This Keynote will then address the challenges in additive and subtractive microfabrication, convective and evaporative thermal transport, thermal and electrical co-design, and physics of failure modeling inherent to the Gen3 Embedded Cooling paradigm.

  AvramDr. Avram Bar-Cohen is an internationally recognized leader in the development and application of thermal science and engineering to microelectronic and optoelectronic systems. In his role at the Defense Advanced Projects Agency (DARPA) and through his professional service in IEEE and ASME, he has defined and guided the field of thermal packaging and facilitated the emergence of high reliability consumer electronics, computing platforms, and microwave communication and radar systems. His research and publications, as well as short courses, tutorials, and keynote lectures, on air-cooled card cages and heat sinks, along with direct liquid cooling of microprocessors and RF components, have helped to create the scientific foundation for the thermal management of micro- and nanoelectronic components and systems. He is the sitting President of the Assembly for International Heat Transfer Conferences. He is an Honorary member of ASME, and Fellow of IEEE, as well as Distinguished University Professor in the Department of Mechanical Engineering at the University of Maryland. From 2001 to 2010 he served as the Chair of Mechanical Engineering at Maryland and is currently on leave to DARPA. Bar-Cohen's honors include the Luikov Medal from the International Center for Heat and Mass Transfer in Turkey (2008), ASME's Heat Transfer Memorial Award (1999), Curriculum Innovation Award (1999), Edwin F. Church Medal (1994) and Worcester Reed Warner Medal (2000), and the Electronic and Electrical Packaging Division's Outstanding Contribution Award (1994) as well as the InterPack Achievement Award (2007). Bar-Cohen was the founding chair of the IEEE Intersociety Conference on Thermal Management in Electronic Equipment (ITHERM) in 1988 and was recognized with the IEEE CPMT Society's Outstanding Sustained Technical Contributions Award (2002), the ASME/IEEE ITHERM Achievement Award (1998) and the THERMI Award from the IEEE/Semi-Therm Conference (1997). Bar-Cohen has co-authored Design and Analysis of Heat Sinks (Wiley, 1995) and Thermal Analysis and Control of Electronic Equipment (McGraw-Hill, 1983), and has co-edited 16 books in this field. He has authored/co-authored some 400 journal papers, refereed proceedings papers, and chapters in books; has delivered 65 keynote, plenary and invited lectures at major technical conferences and institutions, and he holds 8 US and 3 Japanese patents. He has advised to completion 65 PhD and master's students at the University of Maryland, the University of Minnesota and the Ben Gurion University (Beer Sheva, Israel), where he began his academic career in 1972. From 1998-2001 he directed the University of Minnesota Center for the Development of Technological Leadership and held the Sweatt Chair in Technological Leadership. 


Bahgat Sammakia, Interim Vice President for Research, Binghamton University
  BahgatDr. Bahgat Sammakia, a distinguished professor of mechanical engineering, is the interim vice president for research. A former IBM senior technical staff member, Sammakia joined Binghamton's faculty in 1998. He is the founding director of the Small Scale Systems Integration and Packaging Center, a New York State Center of Excellence, and is the director of the Energy-Smart Electronic Systems Center, a NSF I/UCRC founded in 2011 with a focus on reducing the energy consumed by data centers around the world. Sammakia earned his bachelor's degree from the University of Alexandria in Egypt and his master's and doctoral degrees from the University at Buffalo. He is a fellow of the American Society of Mechanical Engineers and a senior IEEE member. Sammakia, editor of the ASME Journal of Electronic Packaging, holds 14 U.S. patents and has published more than 180 peer-reviewed technical papers.
Speaker: Bin Yu, SUNY Albany, Professor

Graphene-Enabled Electronics: Devices and Interconnects

Discovered only eight years ago, graphene (2D carbon nanostructure) and its derivative material systems have received significant amount of research interest from both academia and industry. These emerging nanostructures exhibit unique physical, electrical, thermal, and mechanical properties due to special structural configuration, energy band diagram, and relevant physical phenomena such as Dirac fermion ballistic transport and quantum confinement. This talk introduces basic structure, material process, and key properties of graphene, as well as the potential areas of major technological impacts. The latest research in my lab will be presented, particularly in the field of graphene-based electronics in the "Post-Silicon Era", including demonstration of graphene transistors, interconnects, and circuits. Research directions, challenges, and near-future breakthrough opportunities will be highlighted.

  Bin YuDr. Bin Yu received Ph.D. in Electrical Engineering from University of California at Berkeley. He is Professor in the College of Nanoscale Science & Engineering, State University of New York, Albany, with research interest in energy-efficient "green" electronics, 2D carbon electronics, self-assembly, nano-photovoltaics, and emerging micro/nano devices. He authored or co-authored 5 book/book chapters, published over 150 research papers, and delivered more than 60 invited talks to international conferences, academia, and industry. A prolific inventor, he has over 200 U.S. patents under his name. He is IEEE Fellow, IEEE Electron Device Society Distinguished Lecturer, and a recipient of IBM Faculty Award. He served as Editor of IEEE Electron Device Letters, Associate Editor of IEEE Transactions on Nanotechnology, Editor of Nano-Micro Letters, Consulting Professor of Electrical Engineering at Stanford University, Guest Professor at Beijing University, and on the advisory committees / organizing committee / invited panels of many international conferences and professional organizations. He served also as senior consultant to venture capital, technology law firm, nanotech startup, and semiconductor companies in Silicon Valley.
Speaker: Bruce Murray, SUNY Binghamton University, Professor

Reduced order models for thermal analysis of data centers

Detailed modeling the thermal environment of data centers, including prediction of airflow and temperature distributions, is generally a time-consuming process using full-scale computational fluid dynamics analysis. Reduced order models are necessary in order to provide real-time assessment of optimum operating conditions for data centers to improve energy efficiency. An overview of existing reduced order models will be presented and the advantages and disadvantages of each approach discussed. Application examples will be used to show how reduced order modeling can be used in the development of real-time thermal analysis tools for data centers.

   BruceBruce T. Murray received the B.S. and M.S. degrees in mechanical engineering from Rutgers University in 1978 and 1980, respectively, and the Ph.D. degree in mechanical engineering from the University of Arizona in 1986. Earlier in his career he was a Member of Technical Staff at Bell Laboratories where he was involved in system thermal management and reliability. He also was a research engineer at the National Institute of Standards and Technology (NIST). Currently he is a professor of mechanical engineering at the State University of New York at Binghamton. He teaches and conducts research in the areas of computational modeling, transport sciences and materials processing. He has authored or co-authored over 100 technical publications, and is a member of APS, ASME and ASEE.
Speaker: Charles Woychik, Invensas Corporation, Director of Marketing and Technology

3DIC Markets and Technology Drivers

This presentation will discuss the technology requirements for the fast growing mobile markets and the corresponding 3D IC packaging technologies that are required. The reasons these applications need to use through silicon via (TSV) based 3D IC packaging technology to meet system requirements will be overviewed. The technology choke points that need to be overcome to enable high volume manufacturing will be detailed.

  Charles Woychik is Director of Marketing and Technology for Invensas Corporation™, a wholly owned subsidiary of Tessera® Technologies Inc. (Nasdaq: TSRA). He draws from 25 years of experience in the area of microelectronics packaging, and his extensive knowledge of the design, materials selection and processes used for microelectronics packaging applications ranges from high-performance computer processors to low-cost mobile applications. Prior to Invensas, Chuck worked for General Electric Global Research and Advanced Semiconductor Engineering, after spending the first 18 years of his career with IBM. He holds a doctorate and Master's of Science degree in Materials Science and Engineering from Carnegie-Mellon University. He has a Bachelor's of Science degree in Materials Science from the University of Wisconsin, Madison. Chuck has numerous publications and 42 patents to his credit.
Speaker: David Altman, Raytheon Integrated Defense Systems, Sr. Principal Mechanical Engineer

Vapor Chamber Heat Spreaders for High Power and Packaging Density Electronic Systems

This presentation reviews the development of low profile CTE-matched vapor chamber incorporating high heat flux bearing, low thermal resistance evaporator wick structures. The use of novel micro and nanostructured material systems and comparative performance to alternative solid conductor solutions will be discussed.

  DaveDavid H Altman is a Mechanical Engineer in the Advanced Technology Programs Directorate of Raytheon Integrated Defense Systems. His work focuses on development of new thermal management and energy system technologies. David holds BS and MS degrees from Rensselaer Polytechnic Institute and Boston University. He has authored multiple peer reviewed technical publications and holds two US patents.
Speaker: Evan Colgan, IBM T.J. Watson Research Center, Research Staff Member

Measured Thermal Resistance of Microbumps in 3D Chip Stacks

The thermal resistance of Pb-free ~25 micron diameter and ~16 micron tall microbumps with pitches of 50, 71, and 100 micron have been measured with and without underfill in four-high chip stacks. With underfill, the unit thermal resistance values were 8.0, 15.5, and 19.0 C-mm^2/W for 50, 71, and 100 micron pitch microbumps, respectively. Without underfill, the corresponding unit thermal resistance values were 16.9, 35.3, and 53.1 C-mm^2/W.

  EvanEvan G. Colgan received a BS in Applied Physics from Caltech in 1982 and a PhD in Materials Science from Cornell in 1987. Dr. Colgan joined IBM in 1987 and worked on silicides, selective CVD-W, diffusion barriers, and both Cu- and Al-based chip wiring. He transferred to IBM Research as a Research Staff Member in1995 to manage the TFT processing dept, and subsequently worked on a number of display related projects. He joined the packaging area in 2001 and has worked on optical packaging, high performance liquid cooling including silicon microchannels, super computer packaging, and 3D chip stacks. Dr. Colgan has over 100 technical publications, 118 issued US patents, and is a member of APS, MRS, and a Senior Member of IEEE.
Speaker: Hendrik Hamann, IBM Research, Research Staff Member and Manager

Data Center Measurement and Management Technologies

The energy efficiency of data centers and telecommunication facilities can be largely determined by the extent to which "best practices" are implemented in the operations. In particular, the power consumption of the cooling system can be a significant fraction of the total power needs, which is dominantly governed by the placement of the IT equipment, the chilled air flow control mechanisms as well as the implementation of innovative new technologies such as air side economizing, various air flow management solutions, variable frequency drive fans etc. This presentation will summarize and highlight the development and deployment of IBM's Measurement and Management Technologies (MMT) and describe the results at over 200 DCs.

  hamannDr. Hamann is currently a Research Manager in the Physical Sciences Department at the IBM T.J. Watson Research Center, Yorktown Heights, NY. Since 2001 he is leading the Physical Analytics program in IBM Research, first as a Research Staff Member and currently as a Research Manager. His current research interest includes energy management of large scale computing systems and buildings. He has authored and co-authored more than 70 peer-reviewed scientific papers and holds over 35 patents. Dr. Hamann is an IBM Master Inventor and has served on governmental committees such as the National Academy of Sciences and as an industrial advisor to Universities. He is a member of the American Physical Society (APS), Optical Society of America (OSA), The Institute of Electrical and Electronics Engineers (IEEE) and the NY Academy of Sciences.
Speaker: Hongwen Zhang, Indium Corporation, Research Metallurgist

Reliability Of BiAgX Solder As A Drop-In Solution For High Temperature Lead-Free Die-Attach Application

BiAgX paste, a mixed solder powder paste, shows the melting temperature above 260oC after reflow, which satisfies the temperature requirement for semiconductor and power die attachment for consumer electronics. In the paste system, the metal powders are composed of a high melting alloy powder as majority and the additive powder as minority. The additive solder improves the wetting between Bi and various surface finish materials by its aggressive reaction with the surface finish materials during soldering. As a result, the improved wetting, the associated low voiding and the insensitive IMC layer thickness upon aging have been observed [1]. The bond shear strength of as-reflowed BiAgX joints between Ti/Ni/Au plated Si die and Cu substrate is up to 44% higher than the high lead solder Pb5Sn2.5Ag. After aging at 200oC for 500 hrs, the bond strength of BiAgX shows only minor change while the bond strength of high lead one drops 26%. After 2000 cycles of TCT tests from -55oC to 125oC, BiAgX exhibits the bond shear strength up to 6.1 times of Pb5Sn2.5Ag. Both well-dispersed micron-size Ag particles and Ag-rich phases along the boundaries of Bi colonies have been observed in BiAgX joint. Both Ag-rich phases constrain the dislocation movement in Bi matrix and contribute to the higher bond strength of BiAgX joint. The stepwise fracture surface features surrounding the Ag particles and the AgSn phase along the step edges on the fracture surface evidenced the reinforcement from both types of Ag phases.

  HongwenDr. HongWen Zhang is a Research Metallurgist in Indium Corporation's Research & Development Department. His focus is on the development of the lead-free solder materials and the technologies for high temperature applications. Dr. HongWen Zhang has a bachelor's degree in Metallurgical Physical Chemistry, a master's degree in Mechanical Engineering, and a PhD in Material Science and Engineering from Michigan Technological University. He has published more than 20 journal and conference articles in the field of metallurgy, materials science and engineering, physics, and mechanics. He was also invited as a peer reviewer for numerous journals. Dr. HongWen Zhang has a Six-Sigma Green Belt from the Thayer School of Engineering at Dartmouth College. He is also a certified IPC Specialist for IPC-A-600 and IPC-A-610D.
Speaker: James Lu, Rensselaer Polytechnic Institute, Prof.

Advances in Packaging Technologies for LED-Based Smart Lighting Systems

Light-emitting diodes (LEDs) constitute a rapidly evolving and fast growing technology, leading to replacement of incandescent bulbs and compact fluorescent lights now, and smart lighting systems in future. We envision that the future smart lighting systems can synthesize the light for the benefit of humanity, and engineer the light for energy efficiency, health, and productivity. To that end, the packaging technologies must be developed to integrate optical, thermal and electrical materials with LEDs and sensors for luminaire manufacturing, so the light can be controlled and used for communication and human health. This presentation will highlight the recent advances in packaging technologies for LED-based smart lighting systems. In particular, our research progress in high index encapsulants for light extraction, thermal management, photonic crystal and nano-structures for advanced luminaire design, and high-speed chip transfer and high speed chip assembly on large flexible substrate will be discussed.

  Prof. James Jian-Qiang Lu, the first IEEE Fellow "for contributions to three-dimensional integrated circuit (3D-IC) technology" and an IMAPS Fellow and Life Member, has been working on 3D hyper-integration technology for more than a decade at Rensselaer Polytechnic Institute. He has more than 200 publications in micro/nano-electronics area from theory and design to materials, processing, devices, integration and packaging. His research interests include large area assembly of LEDs, power devices, micro-nano-electronics for future chips, biomedical devices, and 3D hyper-integration of smart systems. He served as general chair, technical chair, workshop chair, session chair, panel moderator and panelist for many conferences.
Speaker: Jeremy Muldavin, MIT Lincoln Laboratory, Assistant Group Leader

Advanced Packaging and 3D integration for MEMS and Integrated Circuits

This talk will cover advanced packaging and 3D integration technologies and research developed at MIT Lincoln Laboratory for MEMS, advanced integrated circuits, and imagers. These packaging technologies are enabling for MEMS devices, offering controlled ambient and a high-performance RF package as well as the ability to integrate MEMS/NEMS with CMOS devices using a 3D integration approach. The wafer scale, tier-by-tier, 3D integration approach developed at MIT Lincoln Laboratory has been utilized for advanced image sensors and read out integrated circuits (ROIC) as well as mixed-material integration and has achieved the highest density 3D interconnect demonstrated to date. Some highlights of reliability experiments on RF MEMS devices will also be presented.

  JeremyJeremy Muldavin received his BSE in Engineering Physics from the University of Michigan in 1995 where he performed research in the area of high energy spin physics. He went on to receive his MSE and PHD (2001) in Electrical Engineering with a major in Electromagnetics and a minor in Communications. His graduate research focused on micro-machined circuits and devices for RF and millimeter-wave circuit and antenna applications. He is currently an Assistant Group Leader of the Advanced Silicon Technology Group at MIT Lincoln Laboratory where he has continued his interest in RF micro-electro-mechanical-systems (MEMS) design, fabrication, and modeling as well as 3D integrated circuits, advanced read-out integrated circuits (ROIC) and flexible electronics. Dr. Muldavin has served for 9 years on the IEEE Radio & Wireless Symposium Steering Committee, for four years as a chair of the IEEE MTT-S Boston Section, and served as the Registration Chair for the 2009 IEEE International Microwave Symposium.
Speaker: Jim Watkins, University of Massachusetts, Professor

Functional Devices via Additive Driven Self-Assembly and Nanoimprint Lithography: Towards Solution-Based R2R Fabrication

Roll-to-roll (R2R) technologies provide a route towards continuous production of flexible material and devices with high throughput and low cost. The NSF Center for Hierarchical Manufacturing (CHM) at University of Massachusetts Amherst, a National Science Foundation supported nanotechnology center, is developing materials and processing approaches to enable the fabrication of nanotechnology enabled devices on a R2R platform. Specifically we employ additive-drive self-assembly to produce well-ordered polymer/nanoparticle hybrids materials that can serve as active layers in a device, have developed simple and effective routes towards substrate planarization, and employ R2R nanoimprint lithography for device scale patterning. Our newly constructed R2R processing facility includes a custom designed, precision R2R UV-assisted nanoimprint lithography (NIL) system and hybrid nanostructured materials coaters. Here we illustrate the capabilities of these approaches by the fabrication of floating gate field effect transistor memory devices. The charge trapping layer is comprised of well-ordered polymer/gold NP composites prepared via additive-driven self-assembly; the addition of gold nanoparticles that selectively hydrogen bond with pyridine in poly(styrene-b-2-vinyl pyridine) copolymers yields well-ordered hybrid materials at gold nanoparticle loadings of more than 40 wt%. The charge trapping layer is sandwiched between a dielectric layer and a poly(3-hexylthiophene) semiconductor layer. We can achieve facile control of the memory windows by changing the density of gold nanoparticles. The devices show high carrier mobility (> 0.1 cm 2/Vs), controllable memory windows (0~50V), high on/off ratio (>105) between memory states and long retention times. Strategies for patterning of the device using NIL and incorporation of solution coat-able high k dielectric layers will be discussed.

  JimJim Watkins is a Professor of Polymer Science and Engineering and Director of the Center for Hierarchical Manufacturing, a National Science Foundation Nanoscale Science and Engineering Center (NSEC) at the University of Massachusetts, Amherst. Professor Watkins received his B.S. and M.S. degrees in Chemical Engineering from the Johns Hopkins University and his PhD in Polymer Science and Engineering from the University of Massachusetts. He joined the Chemical Engineering faculty at UMass in 1996 and the Polymer Science and Engineering Faculty in 2005. He is the recipient of the Camille Dreyfus Teacher-Scholar Award and a David and Lucile Packard Foundation Fellowship for Science and Engineering. 
Speaker: Kamal Sikka, IBM, Manager and STSM

Package Level Thermal-Mechanical Challenges

The proposed talk will address some of the thermal-mechanical challenges encountered at the package level. Primary challenges include higher power density, compressed temperature budgets, mechanical expansion mismatch, form factor complexity and unit / development cost. Solutions to some of the challenges will also be discussed.

  KamalDr. Kamal Sikka is the manager of the package thermal-mechanical modeling and development team at IBM Microelectronics. He obtained his PhD degree in Mechanical Engineering from Cornell University in 1997. He started his IBM carrier working on TIM gap reduction techniques and thermal tester development. In 2002, he took over the management of the modeling and thermal development team dedicated to high-end servers and OEM gaming consoles.
Speaker: Liang-Yu Chen, OAI/NASA GRC, Senior Scientist

Alumina Based 500C Electronic Packaging Systems and Future Development

NASA space and aeronautical missions for probing the inner solar planets as well as for in situ monitoring and control of next-generation aeronautical engines require high-temperature environment operable sensors and electronics. A 96% aluminum oxide and Au thick-film metallization based packaging system including chip-level packages, printed circuit board, and edge-connector is in development for high temperature SiC electronics. An electronic packaging system based on this material system was successfully tested and demonstrated with SiC electronics at 500C for over 10,000 hours in laboratory conditions previously. In addition to the tests in laboratory environments, this packaging system has more recently been tested with a SiC junction field effect transistor (JFET) on low earth orbit through the NASA Materials on the International Space Station Experiment 7 (MISSE7). A SiC JFET with a packaging system composed of a 96% alumina chip-level package and an alumina printed circuit board mounted on a data acquisition circuit board was launched as a part of the MISSE7 suite to International Space Station via a Shuttle mission and tested on the orbit for eighteen months. A summary of results of tests in both laboratory and space environments will be presented. The future development of alumina based high temperature packaging using co-fired material systems for improved performance at high temperature and more feasible mass production will also be discussed.

  Liang-YuLiang-Yu Chen received the B.S. degree in physics from Fudan University, Shanghai, P.R. China in 1982, and the M.S. and Pd.D. degrees in experimental condensed matter physics from Case Western Reserve University, Cleveland, Ohio, in 1989, and 1994, respectively. After graduation, he joined the NASA Glenn Research Center, Cleveland, Ohio, as a National Research Council Fellow studying surface and interface stability of silicon carbide based high temperature chemical sensors to improve device performance, and understand device failure mechanisms at high temperatures. Currently, he is a Senior Scientist at Ohio Aerospace Institute, and supports the high temperature electronic packaging research program at NASA Glenn Research Center. His major research interests include materials, structure, process, and testing of packaging technologies for silicon carbide electronics and sensors for applications in high temperature and other harsh environment.


Ljubisa Stevanovic, GE Global Research, Advanced Technology Leader
  StevanovicLjubisa Stevanovic earned his M.S. and Ph.D. degrees in Power Electronics from Caltech. He has been with GE Global Research since 1993. In his current role of Advanced Technology Leader, Ljubisa leads company's development of Silicon Carbide (SiC) technology, including power devices, advanced packaging and power conversion applications. Under his leadership, the SiC program has demonstrated MOSFET performance and reliability ahead of competing devices and developed power packaging and thermal management technologies ideally suited for fast-switching, high temperature SiC devices. These technologies will impact a range of applications, including energy-efficient transportation, datacenters, medical imaging, and grid-integrated renewables. Ljubisa was recently recognized as one of ten 2012 Heroes of Growth by Jeff Immelt. The awards highlight some of the great leaders who are doing amazing things for the company.
Speaker: Luc Fréchette, Université de Sherbrooke, Professor

Power MEMS and their packaging challenges

Microelectromechanical systems (MEMS) offer an alternative approach to traditional batteries to meet the challenge in powering portable and distributed applications. The novel solutions under development implement thermal, chemical, and electromechanical energy conversion principles at small scale. The presentation will cover microturbine and other microengine technologies for waste heat harvesting from automobile exhaust gases or industrial processes. Micro fuel cells and vibration energy harvesting piezoelectric devices will also be discussed, as replacements for batteries. Focus will be on the packaging challenges raised by these unique devices, including the need to interface with hot or cold sources, manage fluids, and last for extended periods of operation. Challenges in common with thermal management of other semiconductor devices (solar cells, microelectronics) and packaging of harsh environment sensors will also be highlighted.

   LucDr. Luc G. Fréchette is the Canada Research Chair in Microfluidics and Power MEMS, and professor at the Université de Sherbrooke (Canada). His area of expertise is microelectromechanical systems (MEMS) with an emphasis on thermal, chemical, and fluidic applications for sensing, actuating, and power generation. He received his Ph.D. from MIT in 2000 for the design and fabrication of MEMS-based energy conversion microsystems. He started his academic career on the Columbia University faculty in 2000, and moved his research activities to the Université de Sherbrooke (Canada) in 2004. His research activities include MEMS heat engines (microturbines), micro fuel cells, micro energy harvesting devices, as well as microfluidics and MEMS for cooling and sensing in harsh environments. Dr. Fréchette contributes to the development of this field through his active involvement in the organization of international conferences (PowerMEMS; Transducers) and over 70 technical and scientific publications.
Speaker: Marc Papageorge, ICINTEK LLC, President and Founder

MEMS Packaging – A Key Differentiator for Success

With double-digit growth forecasted for the MEMS industry, more MEMS devices and sensors are finding applications into the global market place. Smart phones, handheld gaming devices and consoles, and automotive applications are leading the charge. With devices on the market ranging from pressure sensors, RF-MEMS, accelerometers, and gyroscopes; to microphones, micro-actuators, compasses, CMOS image sensors, chemical sensors, microfluidics, mirrors, and displays, there's no doubt that MEMS are growing fast. How can the industrial ecosystem address how future visions will be realized through the heterogeneous integration of MEMS and ICs. This talk will address the broad range use of MEMS and how packaging technology is the key to the success to bring MEMS applications to the market. This does not only include type of package one uses but the materials, process, and integration comes together in the package that is used.

  MarkMarc Papageorge is President and Founder of ICINTEK LLC, a consulting service firm in the San Francisco Bay area since 2003, with a focus on backend assembly and test supporting start-ups and IDM's operations, materials, packaging and test for Semiconductors and MEMS. He is currently consulting for a variety of worldwide well known electronic companies in the area of MEMS, WLP, & SIP processes and packaging. He has vast experience in business management and subcontract manufacturing services in a variety of market segments in the high technology sector. Papageorge help start-up AIT as Vice President of Marketing and Business Development, which was sold to Unisem Corp. out of Malaysia. He was Vice President of Operations/Technology and Business Development at ASAT LTD. During his tenure in Hong Kong he implemented and established the entire product line of array packaging and QFN products and drove new product and materials developments. Mr. Papageorge worked at Motorola Inc. where he was part of the team whom invented and implemented the Ball Grid Array. He holds 10 granted patents, 7 engineering awards, and published numerous papers in the semiconductor materials and I.C. packaging field. Papageorge holds a master's degree in materials science and engineering from the Georgia Institute of Technology and a bachelor's degree in materials science and engineering from the University of Florida.
Speaker: Mark Christensen, Prismark, Principal Consultant

Market and Technology Trends of Mobile Electronics

Mobile electronics, especially smartphones and tablets, are now key driving forces in the electronics industry. On the market side, they are re-shaping business models and industry structures, and are thus naming new winners and losers throughout the supply chain. With respect to technology, the need for processing power and battery life in an ultra-portable form factor is driving the demand for advanced component and packaging technologies.

  MarkMark Christensen joined Prismark in 1992 and has worked on a wide variety of custom projects for clients throughout the supply chain of the electronics industry. Early on, Mark established Prismark's Teardown Analysis Program in conjunction with the IEEC at Binghamton University. For the past ten years his primary focus has been on communications—wireless and wired— with custom projects investigating opportunities for suppliers of wireless systems, RF modules, and optoelectronics assemblies. Mark is responsible for Prismark's Wireless Technology Report, a quarterly report that analyzes market and technology trends of RF wireless systems, modules, and components. Mark Christensen has B.S. and M.S. degrees in the physical sciences from the University of Konstanz in Germany, as well as a Masters degree in Business Policy from the State University of New York at Stony Brook.
Speaker: Nathan Gill, BAE Systems, Senior Hardware Engineer

Insulated Gate Bipolar Transistors (IGBT) in Hybrid Electric Vehicle (HEV) Applications

IGBTs are a critical component in hybrid electric drivetrains. This presentation will cover IGBTs and their role in hybrid electric vehicles as well as typical duty cycles seen by this component. The wear out mechanisms of IGBTs will be discussed and a method to predict component life.

  NathanNathan Gill graduated in 2008 from Binghamton University with a BS in Mechanical Engineer. He received his MS in Mechanical Engineering from Binghamton University in 2011. He was accepted to the Engineering Leadership Development Program (ELDP) at BAE Systems in 2008 and has worked at BAE Systems the last four years. He has worked on both series and parallel hybrid electric systems as well as Full Authority Digital Engine Controls (FADEC). Over the last year he has taken a role as an analyst performing research on IGBTs in hybrid electric applications.
Speaker: Patrick McCluskey, University of Maryland, Associate Professor

Solder and Die Attach for High Temperature Electronic Packaging

The RoHS ban of lead from electronics has pushed the industry to find lead-free alternatives. This is true even for high temperature applications, where high lead solders have typically been used. This paper will present two ongoing studies that address the need for both chip and component attach that can survive high temperature operation and wide temperature range cycling. The first study focuses on the durability of lead-free component attach under combined temperature cycling and vibration for applications above 125C. Quad flat packs (QFP) and 2512 chip resistors were reflowed on ENIG finished polyimide printed circuit boards with commercially available SAC305 and with versions of SAC305 containing intentional fourth element doping. The doped alloys were chosen because of previously published results showing reduced intermetallic formation in solders containing these elements. Isothermal aging for up to 500 hours was performed to measure the interfacial intermetallic thickness, and characterize intermetallic compounds. An assessment was then performed featuring thermal cycling intermixed with vibration cycling to determine the most durable solder alloy. The second study focuses on the manufacture and temperature cycling durability of transient liquid phase sintered die attach joints made with different combinations of a high melting point metal and a low melting point semimetal. Results will be shown describing the effect of different compositions and reflow profiles on percent conversion and voiding. Shear test results will demonstrate joint strength at temperatures up to 500C.

  PatrickDr. Patrick McCluskey (Ph.D., Materials Science and Engineering, Lehigh University) is an Associate Professor of Mechanical Engineering at the University of Maryland, College Park, where he conducts research at the Center for Advanced Life Cycle Engineering (CALCE) in the areas of thermal management, reliability, and packaging of electronic systems for use in extreme temperature environments and high power applications. Dr. McCluskey has published more than 100 refereed technical articles on these subjects, and has edited three books. He has also served as technical chairman for multiple international conferences and workshops. He is an associate editor of the IEEE Transactions on Components and Packaging, a fellow of the International Microelectronics and Packaging Society (IMAPS), and a member of ASME, IEEE, and SAE.
Speaker: Paul Franzon, NCSU, Professor

Design of 3D Specific Systems

3D stacking and integration with TSVs can provide significant system advantages in terms of power, scale, cost and performance. This talk will cover what we have learned at NCSU over the past five years putting together CAD flows for 3DIC design and designing multiple 3DIC chips in the Lincoln Labs and Tezzaron 3D processes. These designs focus on two general approaches – vertically partitioned digital systems and miniature sensors. The digital systems investigated focus on DSP applications, mobile graphics and sensors for Food Safety and bio interfacing. Issues to be covered in detail include 3D motivation, system engineering, floorplanning and partitioning, thermal analysis and CAD flow. At NCSU, we have put together a 3D CAD flow intended to take a design from initial system concept to tape-out. This flow relies largely on 2D point tools but several 3D enhancements have been investigated. This flow has been exercised in several MPW runs coordinated by Lincoln Labs and Tezzaron. Finally, outstanding issues in 3D design will be summarized and prioritized.

   PaulPaul D. Franzon is currently a Professor of Electrical and Computer Engineering at North Carolina State University. He earned his Ph.D. from the University of Adelaide, Adelaide, Australia. He has also worked at AT&T Bell Laboratories, DSTO Australia, Australia Telecom and two companies he cofounded, Communica and LightSpin Technologies. His current interests center on the technology and design of complex systems incorporating VLSI, MEMS, advanced packaging and nano-electronics. He has lead several major efforts and published over 200 papers in these areas. In 1993 he received an NSF Young Investigators Award, in 2001 was selected to join the NCSU Academy of Outstanding Teachers, in 2003, selected as a Distinguished Alumni Professor, and in 2005 won the Alcoa award. He is a Fellow of the IEEE.
Speaker: Pedro Quintero, University of Puerto Rico-Mayaguez, Assistant Professor

Die attach techniques for high temperature/harsh environment packaging: A shifting melting point approach

There is an increasing demand for electronics that can operate reliably in harsh environments such as high temperature and high power. Relaying on active cooling is becoming a limiting factor, therefore a microsystem that can yield its intended function while operating "hot" is crucial. Wide band-gap (WBG) semiconductors, such as SiC, have demonstrated to perform at temperatures well above the traditional limits of silicon; however there are many challenges that affect the realization of these electronic systems. Of particular interest is the need to provide a reliable die attach that can withstand the expected application conditions which may include temperatures above 200C and high voltages/currents. In this work we will present our current efforts on the development and characterization of novel die attach materials and manufacturing processes aimed at providing a solution for the fundamental problem of solder reflow. When using a metallic solder, the processing temperature must be above the melting point of the solder and the maximum operational condition has to be below it so that no re-melting occurs. This condition imposes a fundamental limitation for reflow, i.e. To < Tm < Tp; where To is the operation temperature, Tm is the melting point of the attach material, and Tp is the processing temperature during assembly. In order to take advantage of SiC devices, a high To is desired without the need to use a braze which will require an elevated processing temperature. We will present three approaches in which a low processing (Tp) temperature is used to produce a high temperature resistant material. The first technique relies on the formulation of a simple Ag nanoparticle paste that can be processed at 300°C that can survive future high temperature excursions. The second method is transient liquid phase sintering of Ag and In powders in which a shift in melting point is obtained during processing. The last approach is solid liquid inter-diffusion of Au and Au-Sn deposited by jet vapor deposition and assembled by vacuum reflow. Details of the fabrication, together with metallurgical characterization and thermal analysis will be presented.

  PedroDr. Pedro Quintero received a BS and MS in Mechanical Engineering from the University of Puerto Rico. After graduation Pedro joined Intel Corp where he worked three years as a reflow and wave solder process engineer. He then served 5 years at Hewlett Packard where he was part of the process technology development group. In 2005 he enrolled in the University of Maryland's PhD program where he worked in packaging of high temperature electronics as part of his research in CALCE. Since 2008 Dr. Quintero has been working as an assistant professor of Mechanical Engineering at the University of Puerto Rico where he teaches courses on Manufacturing Processes, Creative Design and Electronic Packaging. His research area focuses on interconnections for extreme and Pb-free electronics.
Speaker: Peter Brofman, IBM, Distinguished Engineer

Materials Science Challenges in the Packaging Technology Roadmap

This paper considers the critical role played by materials science in advancing the technology roadmap for electronics packaging. Evolving trends in packaging technology are discussed, along with a look at IBM's roadmap and the associated materials implications. A sampling of recent, real-life materials science issues are reviewed, along with current / potential solutions. Finally, a forecast of what lies ahead is offered. 

  PeterPete Brofman is an IBM Distinguished Engineer in the Semiconductor Research & Development Center (SRDC) Electronic Packaging group at IBM's East Fishkill, NY facility, responsible for Packaging Technology Strategy. He is also Manager, Packaging Research, IBM Watson Research Center in Yorktown Heights, NY. Dr. Brofman holds a BS, MS and PhD in materials science, as well as an MBA, from RPI, and joined IBM in 1980. He has several formal awards, over 20 technical papers and 18 US patents. Pete also serves as the IBM representative on the Semiconductor Research Corporation Technical Advisory Board (SRC-TAB), is a member of the ASM, International, and a member of the IBM Academy of Technology
Speaker: Paul Marchal, IMEC, Director

3D Integration – a corner technology for heterogeneous integration

3D Integration technology is a wafer-level packaging technology that is transforming the roadmap of semiconductor industry at a rapid pace. It provides an alternative for scaling functionality to Moore's law, and in many cases in a more cost-effective way. Today, most 3D products are homogeneously stacked dies: multiple CMOS dies from the same foundry stacked onto an interposer or a stack of DRAM memories. Whereas this application is least challenging to manufacture in the supply chain, the main interest of industry is to use this technology for heterogeneous integration, where the dies built in different technologies and possibly in different foundries are integrated in one package. Heterogeneous integration with 3d offers many benefits from a system-level in terns of form-factor reduction, performance, design flexibility and cost. However, many challenges wafer-level processing challenges remain to build these heterogeneous stacks within the supply chain (thin wafer handling, mechanical stress management & test). We will conclude the talk by explaining remaining challenges and possible solutions based on our experiences with the prototypes built at imec.

  Paul Marchal holds a position as director of technical marketing at imec. He is responsible for defining technology roadmaps for imec's advanced packaging solutions in close collaborations with US customers. Before he initiated and led imec's 3D design initiative and insite program. He received the engineering degree and Ph.D. in electrical engineering from the Katholieke Universiteit Leuven, Belgium in 1999 and 2005 respectively. He has a background that combines technology R&D with system and product development. 
Speaker: Rabindra Das, Endicott Interconnect Technologies, Inc., Principal Engineer

Package-Interposer-Package (PIP): A Breakthrough Package-on-Package (PoP) Technology for 3D-Integration

A new 3D "Package Interposer Package" (PIP) solution is suitable for combining multiple memory, ASICs, stacked die, stacked packaged die, etc., into a single package. Traditional Package on Package (PoP) approaches use direct solder connections between the substrates and are limited to use of single (or minimum) die on the bottom substrate, to reduce warpage and improve stability. For PIP, the stability imparted by the interposer reduces warpage, allowing assemblers of the PIP to select the top and bottom components (substrates, die, stacked die, modules) from various suppliers. This mitigates the problem of variation in warpage trends from room temperature to reflow temperature for different substrates/modules when combined with other packages. PIP facilitiates more space-efficient designs, and can accommodate any stacked die height without compromising warpage and stability. PIP can accommodate modules with stacked die on organic, ceramic, or silicon board subsrates, where each can be detached and replaced without affecting the rest of the package. Thus, PIP will be economical for high-end electronics, since a damaged, non-factional part of the package can be selectively removed and replaced.

  RabindraRabindra Nath Das is a Principal Engineer at Endicott Interconnect Technologies. He holds a MS and Ph.D. in chemistry from Indian Institute of Technology, Kharagpur. His research work focuses in the area of nanotechnology and has experience over fifteen years. He has developed number of advanced nanomaterials for applications ranging from interconnect to laser to embed passive. He has around 95 nano based technical papers and around 50 issued/filed patents.
Speaker: Raj Jammy, Sematech, Vice President
  RajRaj Jammy is Vice President of Materials and Emerging Technologies at SEMATECH, with responsibilities in advanced logic, memory, 3D interconnects, and emerging device technologies. He is responsible for leading the consortium's efforts to tap into emerging technologies with disruptive scaling potential. Prior to this position, Jammy served four years as director of SEMATECH's Front End Processes division, on assignment from IBM. Jammy began his career in the industry at IBM's Semiconductor Research and Development Center in East Fishkill, NY, where he worked on front-end technologies for deep-trench DRAMs. He subsequently became manager of the Thermal Processes and Surface Preparation group in the DRAM development organization. In 2002, Jammy moved to T. J. Watson Research Center in Yorktown Heights, NY to manage IBM's efforts in high-k gate dielectrics and metal gates. Jammy received a doctorate in Electrical Engineering from Northwestern University. He holds more than 50 patents and is an author/co-author of over 250 publications/presentations.
Speaker: Rolf Aschenbrenner, Fraunhofer IZM

Embedding Technologies for Power Electronic Applications

An increasing demand for highly reliable and cost-efficient power electronics is identified in various industry sectors, where control and efficient use of power is required. Dominant driving forces and impulses in Europe are given by automotive applications. Especially the in the upcoming generations of hybrid cars and fully electrical vehicles power modules -400 V, 200A- will be implemented. Besides handling of power the miniaturization of modules is a major topic. In an engine compartment installation space typically is an issue. Therefore small size and high integration level of the modules are needed.

For the fabrication of conventional modules IGBTs (Insulated Gate Bipolar Transistors) and diodes are soldered to DCB (Direct Copper Bond)-ceramics based electrical circuit substrates. Front contacts to the substrates are made by multiple and/or thick Al wire bonds. Ceramic modules are then typically vacuum soldered to water-cooled base plates in order to disperse heat from the module.

The embedding of power switches and controllers into compact modules using PCB (Printed Circuit Board) technologies is a promising alternative approach to the DCB based technology. It bears the potential to improve thermal management by double-sided cooling and at the same time to reduce total thickness of the module. A number of technical challenges and solutions are investigated at present. In order to replace DCB ceramics a structure of thermal laminate material between thick Cu layers has been developed and the capability for thermal conduction and electrical insulation has been evaluated. For the assembly of large power IGBTs of more than 100 mm² size new silver based sintering pastes have been evaluated. They enable a pressure-less sintering at 200 °C, compatible to PCB materials. To handle the high switching current up to 200 A, suitable copper tracks in the PCB are required. The realization of such thick copper lines up to 1 mm thickness requires advanced processing, compared to conventional multilayer PCB production. In order to form complex power systems out of different modules the module to module interconnection by Ag sintering is under development.

  AschenbrennerRolf Aschenbrenner was born in Buchen, Germany. He received the B.S. degree in mechanical engineering from the University for Applied Science, Gießen, Germany, in 1986 and the M.S. degree in physics from the University of Gießen, Germany, in 1991. From 1991 to 1992 he has worked at the University of Gießen in the area of new materials and was engaged in a project for the German Space Lab Mission D2. In 1993, he joined the Research Center for Microperipheric Technologies at the Technical University of Berlin, working in the area of electroless metal deposition. Since March 1994 he has been employed at the Fraunhofer Institute for Reliability and Microintegration Berlin (IZM) where he is presently head of the department System Integration and Interconnection Technologies. From 2000 until 2006 he was Deputy Director of the Fraunhofer Institute IZM and since 2010 he is again Deputy Director of the IZM. On 12 January, 2005 he was awarded the "iNEMI International Recognition Award" (during the Fraunhofer IZM Packaging Day). In September 2010 he was appointed Deputy Director of the Fraunhofer IZM again. As a member of the IEEE CPMT Society Board of Governors Rolf Aschenbrenner has worked as a European representative on the Conference Advisory Board Committee, and has played an active role in the globalization of IEEE CPMT in terms of membership and chapter development. He is a Senior Member of IEEE and served as IEEE CPMT Vice President, Technical and IEEE CPMT Vice President, Conferences. From January 2010 until December 2011 he was IEEE CPMT President.
Speaker: Sandeep Tonapi, Anveshak Technology and Knowledge Solutions, Founder and CEO

Reliability of thin film flexible electronics

The worldwide demand for flexible electronics has been growing at a rapid pace. Flexible electronics has seen its application across multiple industries (medical, automotive, aerospace, consumer electronics, solar etc). In addition to advantages like lightweight and ability to bend, the capability to manufacture flexible electronics in a roll-to-roll manner also provides a low cost solution. The display industry has probably benefitted the most. There is significant potential for application of thin film technology in the solar domain. This talk will focus on reliability challenges for thin film solar modules. In particular, we will discuss the rolling and unrolling process of a thin film (multi-layer stack) and the impact on roll set curl and delamination. A liner static structural analysis will be presented for a 11 layer stack and after identifying the key layers, a detailed non-linear structural analysis will be carried out for the simplified stack. The effect of changing the geometry and material properties (modulus and CTE) will be presented.

  topaniDr. Sandeep Tonapi is the Founder and CEO of Anveshak Technology and Knowledge Solutions based in Chandler, Arizona. Anveshak provides engineering solutions to its customers in the semiconductor, automobile and energy sectors. Prior to founding Anveshak, Sandeep worked at GE for 7 years. He spent the first 5 years in the Micro and Nano Structures Technologies organization at GE Global Research (Schenectady, New York) followed by 2 years at GE Healthcare in Phoenix, Arizona. Sandeep has 28 patents (granted and/or published), has co-authored over 40 papers in journals and refereed conference proceedings as well as given over 20 invited talks. He serves as the Associate Editor for ASME Transactions – Journal of Electronic Packaging and IEEE Transactions – Components and Packaging Technology. He served on the executive committee of ASME's Electronic and Photonic Packaging Division (2005-2011) and served as Program and General Chair for premier ASME and IEEE conferences - InterPACK 2009/2011 and ITherm 2010/2012. Sandeep is a fellow of ASME and a senior member of IEEE. He has received numerous awards during his career including the ASME EPPD Young Engineer Award, Journal of Electronic Packaging Best Associate Editor Award, Whitney Award for Technical Excellence at GE Global Research, Patent Bronze, Silver and Gold Medallion, mentoring award, and the customer centricity award. Sandeep received his PhD from Binghamton University (2001) where his dissertation received the Distinguished Dissertation Award. 
Speaker: Satish Chaparala, Corning Incorporated, Senior Research Scientist

Thermal Management and Reliability of Quantum Cascade Lasers (QCL)

Semiconductor quantum cascade lasers that emit mid-infrared light in the wavelength range of 4 to 9 mm are uni-polar and the laser emission is due to intersubband transitions in a repeated stack of multiple quantum wells. The thermal management of these devices is a challenge. The overheating of the active region (referred to as 'core' ) in these lasers decreases the optical power and ultimately results in laser failure. A detailed finite element (FE) based numerical modeling of the thermal behavior of these devices and the measurements performed to validate the models is presented. The studies include the effect of submount material, mounting schemes such as epi-side down or epi-side up mounting and the effect of core geometry on the thermal impedance. We have also looked at various core designs such as split core. Thermal behavior of QCL is compared with that of conventional semiconductor laser diodes such 978 nm broad area lasers. Life time reliability tests conducted and the results obtained from the tests will be discussed. Lastly, the challenges in the thermal management of QCL are discussed.

  ChaparalaDr. Chaparala received his MS and PhD from SUNY, Binghamton in 2006. His research interests include numerical and experimental analysis in the areas of structural and thermal aspects in the areas of Micro and Opto-electronics packaging. Currently he is working as Senior Research Scientist at Corporate R&D center of Corning Incorporated. He is working on structural mechanics and impact dynamics of Corning specialty glasses used in consumer electronics, thermal management and packaging of laser diodes, etc.
Speaker: Sean Garner, Corning Incorporated, Research Associate

Ultra-Slim Flexible Glass for Electronic Applications

As displays and electronics evolve to become lighter, thinner, and more flexible, the substrate choice continues to be critical to their overall optimization. The substrate directly affects improvements in the designs, materials, fabrication processes, and performance of advanced electronics. With their inherent benefits such as surface quality, optical transmission, hermeticity, and thermal and dimensional stability, glass substrates enable high-quality and long-life devices. As substrate thicknesses are reduced below 200um, ultra-slim flexible glass continues to provide these inherent benefits to high-performance flexible electronics. In addition, the reduction in glass thickness also allows for new device designs and high-throughput, continuous manufacturing enabled by roll-to-roll processes. This paper provides an overview of WillowTM glass substrates and how they enable flexible electronic device optimization.

  SeanSean Garner received a B.Eng. degree in Engineering Physics (Applied Laser and Optics) from Stevens Institute of Technology in 1993 and a Ph.D. degree in Electrical Engineering (Electrophysics) from the University of Southern California in 1998. Since 1998 Sean has been working in the area of materials processing and device prototyping at Corning's Science and Technology center.
Speaker: Shekhar Borkar, Intel, Director of Extreme-scale technologies

Ubiquitous computing in the coming years - Technology challenges and opportunities

Technology scaling will continue, providing abundance of transistors to integrate diverse functions, enabling unprecedented compute capability to enrich our lifestyle. However, it's the same Physics that helped in the past will now pose some barriers, and "Business as usual" will not be an option. This talk will highlight the challenges and opportunities for the compute-continuum, spanning high performance computers in the data-centers to hand-held mobile devices, making computing truly ubiquitous.

  ShekharShekhar Borkar is an Intel Fellow, an IEEE Fellow, and Director of Extreme-scale technologies at Intel Corporation. Shekhar has been with Intel since 1981, worked on the 8051 family of microcontrollers, supercomputers, high performance, low power digital circuits research, and served as the principal investigator of the DARPA funded UHPC project. Shekhar has authored 83 peer reviewed publications in conferences, 31 papers in journals, 56 invited papers and keynotes, four book chapters, and has more than 50 patents issued. He was an adjunct faculty at Oregon Graduate Institute, taught graduate course on VLSI design for more than 10 years. Shekhar holds M.Sc. in Physics from University of Bombay in 1979, and MSEE from University of Notre Dame in 1981.
Speaker: Subhash Shinde, Sandia National Laboratories, Principal Research Staff

Front End of Line Through Silicon Via (FEOL-TSV) Fabrication

3D integration provides important solutions for electronics systems miniaturization, for multiple applications (viz. imaging, high performance computing, communications, and energy). 3D integration offers considerable advantage by combining analog, digital, and other functions in a low-volume solution utilizing vertical die or wafer stacking. Some solutions for die and wafer stacking employ layer to layer vertical interconnects created after complete wafer fabrication. This vias-last approach requires via formation, isolation, and filling processes to be carried out at temperatures that are below 450C to be compatible with typical integrated circuit (IC) metal layers. Also, since the vias are formed last they take up space through all the metal layers in the metal routing layers of the chip, impacting the efficient use of semiconductor 'real estate'. We will describe the approach we have developed to address these issues, viz. a complete process module for creating front end of line (FEOL) through silicon vias (TSVs). We employ Bosch etching to form high aspect ratio vias. After patterning and etch, dielectric isolation of the resulting via is achieved by thermal oxidation of silicon. After dielectric isolation, we use low pressure chemical vapor deposition (LPCVD) to deposit a conformal silicon fill of the etched and lined via. The silicon overburden is removed by CMP. To protect the thermal oxide via liner from wet etches that are common to FEOL processing and to protect the silicon in the via from silicide formation, a silicon nitride barrier is defined to protect the sacrificial silicon and the oxide. After FEOL processing, the FEOL structures are covered by inter-layer dielectric (IMD) films. To expose the silicon that has filled the TSV, contacts are formed using photolithography and plasma etch process.. Once the silicon is exposed, dry processing is used to etch the silicon in the via leaving an unfilled via that is re-filled using tungsten CVD. CMP is used to remove the tungsten overburden. The resulting via is defined by initial patterning and etch processes, the dielectric isolation, and the metallization using tungsten. We have used gate oxide integrity test vehicle wafers to confirm the front-end compatibility of this process module. Concurrently we have also developed a high fidelity modeling approach to understand the stress distribution in 3D integrated structures. This is very important from device performance as well as TSV layout points of view. The modeling process involved three primary steps. In the first, we generated a parameterized geometrical representation of the structure. To accommodate all design features, we used the fabrication layout files and process definitions as the basis of the 3D virtual geometry. The parameterization allowed for the quantification of geometric uncertainties encountered due to processing inaccuracies and variations. In the second step, we developed a mesh generation program to enable high-fidelity finite element analysis. In the third step, we simulated the physical behavior of the body using a nonlinear, 3D finite element model with temperature-dependent material plasticity.

  SaurabhSubhash L. Shinde (PhD Mat Sc. & Eng. Stanford Univ.) is a Principal Research Staff at Sandia National Laboratories working in the area of 3D integration of microsystems, since 2004. Prior to joining Sandia, he was at IBM's Research and Microelectronics divisions for eighteen years At IBM, Subhash was involved in basic research on high temperature superconducting materials, investigating the inter-grain coupling using ac and dc magnetization. He was also involved in developing leading edge thermal solutions for IBM's high end computers using his knowledge of high thermal conductivity materials. At Sandia, Subhash with his team is working on developing advanced architectures that can only be realized by 3D integration (3DI). To develop 3DI he is heading a team to perform leading edge research in all aspects of 3DI technologies. Subhash and his team have published their work at the ECTC conferences, MRS, and at DARPA workshops. In addition, he has been the organizer of five "3D Integration" ECTC sessions. Subhash has over 35 publications, 60 US patents, and 10 international patents. He is also the Editor of two books published by Spring-Verlag, with a third to be published next year.
Speaker: Urmi Ray, Qualcomm, Senior Staff Engineer

Status and Challenges of 3-D Integration using TSVs for Mobile Devices

Users of mobile devices continue to require smaller form factor and more and more integration in semiconductor IC and packaging. This has resulted in many innovations over the last decade. 2.5D TSV interposers and 3D through silicon stacked (TSS) DRAM are now emerging in product applications. We can expect that these first generation 2.5D/3D technologies will continue to evolve toward smaller TSVs, finer pitch tier to tier connections, reduced die thickness, more stacked tiers, and higher bandwidth interfaces. In this talk, I will present updates on the following topics
• Technology summary status
 Equipment readiness - pilot lines going into HVM soon?
 Product announcements - DRAM vendors, interposers
 Standardization - Many activities ramped up in 2011
 Business and pricing issues

  Urmi Ray is currently the technical program manager for QCT'sThrough Silicon Stacking (TSS) program and low cost Si interposer technology. She has been with Qualcomm since 2006, after spending 10+ years at Lucent Technologies Bell Laboratories in NJ working on advanced materials and reliability projects. She has a PhD from Columbia University (NY City).
Speaker: Yong Liu, Fairchild Semiconductor Corp., Senior Member of Tech Staff

Trends of Power Electronic Packaging

Power electronic packaging is one of the fastest changing areas of technology in semiconductor industry due to the rapid advances in power integrated circuit (IC) fabrication and the demands of a growing market in almost all areas of electronic application such as portable electronics, consumer electronics, home electronics, computing electronics, automotive, and high power industry. However, due to the intrinsic high current density, the performance requirement for power products are extremely high, especially in handling harsh thermal and electrical environments. The design rules and material and structure layout of power packaging are quite different from regular memory and digital IC packaging. This talk will present a state-of-art overview of recent advances in power packaging, challenges and opportunities in power design, assembly and reliability. A review of recent advances in power electronic packaging is presented based on the development of power device technology, such as smart power packaging, which integrates the analog, logic and power device. The talk will cover in more detail how challenges in both semiconductor content and advanced power package design and materials have co-enabled significant advances in power device capability during recent years. Extrapolating the same trends in representative areas for the remainder of the decade serves to highlight where further improvement in materials and techniques can drive continued enhancements in usability, efficiency, reliability and overall cost of power semiconductor solutions.

  YongDr. Yong Liu has been with Fairchild Semiconductor Corp in South Portland, Maine since 2001 as a Senior Member Technical Staff from 2008, and a Member Technical Staff from 2004 to 2007, and a Principal Engineer from 2001 to 2004. His main interest areas are advanced analog and power electronic packaging, modeling and simulation, reliability and material characterization. He has been invited to give keynotes talks, presentations and professional short courses at IEEE international conferences Eurosime, ECTC, APM, EPTC, ICEPT, InterPAK and universities and semiconductor industry in US, Europe and China. He has authored and co-authored 2 books, 3 book chapters and over 160 papers in journals and conferences and has held over 40 US patents (35 granted and over 10 pending) in the area of stack/3D/embedded analog and power packaging. Dr. Liu was awarded Alexander von Humboldt Fellowship and studied at Tech University of Braunschweig, Germany in 1994. In 1997, he was awarded Alexander von Humboldt European Fellowship and studied at University of Cambridge, England. In 2000, he worked as a staff opto package engineer at Nortel Networks at Boston. Since he joined Fairchild in 2001, he was awarded Fairchild Key Technologist in 2009, the first Fairchild President Award in 2008, Fairchild Key Technologist in 2006, Fairchild BIQ award in product innovation in 2005, and Fairchild award for power of pen first place in 2004. Dr.Yong Liu is currently IEEE senior member and serves as several technical committees of international conferences.
Speaker: Yogen Utturkar, GE Global Research, Manager of the Electronics Cooling Laboratory

Overview of Electronics Cooling Research in GE

The introduction of differentiating functionalities into GE products often entail higher power densities within its electronics systems/subsystems. For example, more light from LED lamps, higher scanning time and resolution for ultrasound probes, wider MR patient bore, higher onboard computer power on UAVs and reliable operation of power conversion equipment in the subsea environment demand efficient thermal management solutions, which are able to address various impedances along the heat path originating from the semiconductor devices to the ultimate rejection reservoir (air/fuel/chilled water etc.). The presentation will provide an overview of some key technologies developed at GE Global Research in the arena of electronics thermal management and their impact on specific GE products.

  utturkar_yogenDr. Yogen Utturkar is the Manager of the Electronics Cooling Laboratory in GE Global Research. After completing his Ph.D. degree in Mechanical Engineering at the University of Florida, Yogen began his GE career in September 2005 in the area of electronics cooling. Yogen provided technical leadership, innovation, and global engagement on the licensing effort of GE's Dual Cool Jets (DCJ) (commonly known as synthetic jets), a patented and powerful cooling solution for consumer microelectronic products. Yogen and his team were rewarded with a 7-year commercialization agreement between GE and Fujikura Inc. for productizing and proliferating DCJs in world-wide consumer markets. Yogen has also provided technical leadership on developing novel cooling solutions for MRI products and high-lumen LED downlights. In addition, Yogen has also diversely contributed to projects related to residential energy efficiency, multi-stage biomass gasification, and bio-inspired uncooled IR detectors. Yogen has 21 patents filed and 31 internal and external publications to his name.
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Last Updated: 4/26/13