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Confirmed Presenters at 2014 Electronics Packaging Symposium

Speaker   Organization

Azemar, Jerome


Araujo, Ken


Berrigan, Dan

  Air Force Research Lab's

Bottoms, Bill

  Third Millennium Test Solutions

Castracane, James


Chaney Richard

  American Semiconductor

Chiang, Shiuh-Kao


Egitto, Frank

  i3 Electronics

Ellsworth, Mike


Fleischer, Amy


Garner, Sean


Gurumurthy, Charan


Huffman, Alan


Iyer, Subramanian


Kandlikar, Satish


Lee, Ning-Cheng


Lee, Kangwook

  Tohoku University

Li, Tao

  University of Michigan

Liu, Weiping


Macdonald, Eric

  University of Texas - El Paso

Marconnet, Amy


McCluskey, Pat

  University of Maryland

Okabe, Hiroyuki



Patti, Bob



Polinsky, Bill 


MS Kennedy

Poole, Neil



Rae, Alan


Alfred Technology Resources

Ready, Steve



Sammakia, Bahgat


Binghamton University

Schoeller, Harry



Shaddock, Dave


GE Global Research

Shorey, Aric


Smukowski, David

  Sensors in Motion

Spadaccini, Chris


Lawrence Livermore National Lab

Trant, Gerald



Williams, Christopher


Virginia Tech

Woychik, Chuck



Yamada, Tomoyuki




Speaker: Jerome Azemar, Yole
Abstract: Embedded Dies packaging solutions: Technology trends and market forecasts.
  Embedded packages are getting more and more interest from potential customers for a simple reason: It is simply logical to try to embed devices and passives! Indeed, added value in terms of integration, reliability and even cost at system level is clear for manufacturers. Despite the idea being old, the strategy is still lacking success because of long time qualification, few players involved, no standard and customers convincing time. Situation is starting to change with new products and announcements made and strong involvement from some players. One approach especially might change the game rules. Embedding in laminate substrates (PCBs), a process pushed by PCB manufacturers such as AT&S, could create a new supply chain with new players. High volume production has not been reached yet because Embedded Die technologies still have challenges to overcome: multi-sourcing, supply chain organization, technology qualification.... Key customers already qualified some and could open the gates for fast growing packaging market. The presentation will provide an overview of the products announcements, commercialization roadmaps as well as market forecasts per application. Insights and trends into the different embedded die packaging approaches by applications, business models and major players will be reviewed.
  azemarJerome Azemar is currently Market ant Technology analyst at Yole Développement, specialized in Advanced Packaging Business and Semiconductor Manufacturing.
Jérôme has 7 years of experience in the field of semiconductors. Upon graduating from INSA Toulouse with a master's in Microelectronics, he joined ASML and worked in Veldhoven for three years as an Application Engineer, specializing in scanners for photolithography and supporting major semiconductors devices manufacturers. He then honed over a two-year stint as a Process Engineer at STMicroelectronics. While with ST he developed new processes, co-authored an international publication and worked on metrology structures embedded on reticules before joining Yole Développement in 2013. As a market analyst, Jérôme provided several market research and strategy analysis and performed several presentations and market briefings in semiconductors conferences.
Speaker: Ken Araujo, Namics
Abstract: Pre-Applied Materials for 2.5/3D Technology

The age of advanced mobile devices is on the direct horizon, are we ready for it? Less power consumption, faster processing, high reliability, high yield, low cost are words engineers are all too familiar with. 2.5/3D utilizing interposer technology, Thru Silicon Via (TSV), sub-50μm die thickness are a few of the latest techniques engineers use to solve these issues. As technology progresses to smaller process generations, new packaging applications are being demanded. The standard solder reflow process is being pushed by advancements in Cu pillar bumps, thermal compression bonding (TCB) and wafer level / pre-applied materials. This presentation will centralize around the latest advancements in NAMICS Pre-Applied Material, Non-Conductive Paste (NCP), Non-Conductive Films (NCF) and B-Stage No-Flow Underfills (BNUF).


araujoKen Araujo is the Area Manager for NAMICS Technologies. For the past four years, he has been responsible for providing technical and sales support to leading semiconductor and electronic companies throughout the US. Prior to joining NAMICS, he held various positions in the technical service, manufacturing and quality fields. He received his degree in Plastics Engineering from the University of Massachusetts at Lowell and currently resides in southeastern Massachusetts.

Speaker: Dan Berrigan, Air Force Research Lab's
Abstract: Air Force Interests in Flexible Devices and Additive Manufacturing of Functional Materials
  The U.S. Air Force is increasingly tasked to do more with less, which means sustaining assets beyond their expected lifetime, simplifying logistics chains, and developing more agile systems that can serve a broad set of missions. Both flexible electronics and additive manufacturing promise to aid in addressing these challenges by allowing electronics to be embedded into existing or new structures, tailored for particular environments, and produced in small quantities with minimal infrastructure. This talk will describe past and current efforts to utilize flexible electronics and additive manufacturing to create new capabilities in the areas of multifunctional materials (i.e., the marrying of form and function), survivable electronics, and wearable human performance sensors.
  Dan Berrigan is a Research Scientist in the Flexible Materials and Devices Research Team at the Air Force Research Lab's Materials and Manufacturing Directorate. He graduated in with a Ph.D. in Materials Science in 2012 from the Georgia Institute of Technology, and has a Bachelor's degree in Materials Science from the Univ. of Illinois at Urbana-Champaign. Along with Mike Durstock and Ben Leever, he helps lead AFRL's in-house effort in ink and process development for additive manufacturing of functional materials and devices.
Speaker: Wilmer R. Bottoms, Third Millennium Test Solutions
Abstract: A Revolution in Packaging Driven by the Internet of Things and Migration to the Cloud
  The electronics industry is still reacting to the rapid change from personal computers to mobile products as the technology driver. The market for PCs has already fallen below that for mobile devices; evidence of fundamental changes in our industry. RF components, low power processors, power management ICs have all gained share relative to traditional PC components. With mobility transition still underway the revolutionary change in packaging has already started. This revolution is driven by two connected changes in the interaction of society with technology; transition to the cloud and rise of the internet of things. Both demand a revolution in our data networks that will change the data center, the computer center, network architecture and virtually all electronic components they contain. The current solutions for these elements cannot satisfy the future requirements for lower latency, reduced power and increased physical density of bandwidth. At the same time new circuit types such as photonics, MEMS, plasmonics and a plethora of new sensors are expanding global network requirements. Some of the difficult challenges and potential solutions will be discussed.

Dr. Wilmer Bottoms received a B.S. degree in Physics from Huntington College in Montgomery, Alabama in 1965, and a Ph.D in Solid State from Tulane University in New Orleans in 1969 and is currently Chairman of Third Millennium Test Solutions. He has worked as a faculty member in the department of electrical engineering at Princeton University, manager of Research and Development at Varian Associates, founding President of the Semiconductor Equipment Group of Varian Associates and general Partner of Patricof & Co. Ventures.
Dr. Bottoms has participated in the start up and growth of many companies through his venture capital activity and through his own work as an entrepreneur. These include companies in a wide range of industries. Among these companies are: APMT, Business Insurance Company, Chevy's Mexican Restaurants, Credence Systems, Johnny Rockets, Microelectronics Packaging Inc., NanoNexus, SBA Material,  Southwest NanoTechnologies, Tessera, Third Millennium Test Solutions.He has also served on government committees including the Board on Assessment for the National Institute for Standards and Technology and the Technical Advisory Committee to the Export Control Commission. Dr. Bottoms currently serves as:

  • Emeritus Member of the Board of Tulane University
  • Chairman of the Technical Working Group for Assembly and Packaging for the International Technology Roadmap for Semiconductors
  • Chairman of the Technical Working Group for Packaging and Component Substrates for the International Electronics Manufacturing Institute
  • Chairman of the Semiconductor Equipment and Materials International's SEMI Awards Committee
  • Chairman of APMT
  • Chairman of Third Millennium Test Solutions"
Speaker: James Castracane, CNSE
Abstract: Integrating the Animate and Inanimate Worlds: IC Fabrication Methods for Bio Applications
The rapid advances in 3D integration associated with next generation microprocessor development have been leveraged and applied to a variety of biomedical systems. Integrating cells, tissues, biomolecules, etc. with computer chip architectures has yielded numerous biodevices with high sensitivity and specificity for point of care diagnostics, toxin detectors and implantable constructs, among many others. The ability to fabricate mechanical features which are on the same size scale as cellular and even sub-cellular dimensions opens new doors to exploit the natural reaction of cells to selected constituents in their microenvironment. Further, optical, electrical, chemical or biological responses of cells/biomolecules can be monitored and transduced to useful data for analysis using nanoelectronics circuitry. The transition from nano to micro to macroscale completes the link for examining the inner workings of these biological entities. The use of IC fabrication methods allows for wafer scale production and integration to achieve reproducible and low cost systems for biomedical research and treatment. This talk will give an overview of selected Nanobioscience programs at the SUNY College of Nanoscale Science and Engineering (CNSE) which are focused on combining microfluidics, biomolecule immobilization, readout electronics and in vivo cell collection and will be presented against the backdrop of the state of the art IC processing infrastructure at CNSE.
castracaneDr. Castracane is Professor (Founding Faculty) and Head of the Nanobioscience Constellation in the College of Nanoscale Science and Engineering (CNSE) at the University at Albany-SUNY. Dr. Castracane received his BS degree in Physics from Canisius College (1976) and his Ph.D. in Physics from The Johns Hopkins University (1982). Dr. Castracane has received research funding from numerous Federal agencies including NIH, NSF, DOD, DOE, DARPA, and NASA as well as a significant portfolio of State and corporate sponsors. His publication record spans over 150 articles, numerous invited or keynote presentations and 14 patents issued/pending.Prior to joining CNSE in 1998, Dr. Castracane's private sector experience involved positions at high technology R & D companies including Chief Operating Officer at InterScience, Inc. from 1994-98. As Director of the New York State Center for Advanced Technology in Nanomaterials and Nanoelectronics from 2004-2009, Dr. Castracane continued to assist in the development of the business potential of numerous companies through technical interactions and management consulting.
Richard Chaney, American Semiconductor
Enabling Flexible Hybrid Electronics with the FleXform Development Kit
Flexible Hybrid Electronics combines printed electronics with physically flexible silicon ICs to enable unique and revolutionary applications and products. Printed electronics offer rapidly evolving sensors, displays, and other devices. FleX-ICs can deliver the necessary high performance semiconductor features. Other relevant technologies are improving such as physically flexible batteries. What is missing is a common development platform that brings all of the pieces together for integrated technology and product development. American Semiconductor is providing an integrated solution with the FleX Development Kit that includes the physically flexible FleX-MCU and FleX-ADC ICs, a multi-layer Flexible Circuit Board (FCB), a printed sensor, and space for user applied printed sensors, displays, and other add-ons through general purpose I/Os. The presentation will provide technical details of the FleXform Kit as well as an updated status of the FleX Development Kit set for release in late 2014.
chaneyRichard Chaney, General Manager for American Semiconductor has over 20 years of experience in semiconductor technology and management. Mr.Chaney currently manages the FleX Silicon-on-Polymer production line, including product management, process engineering, and research & development. His work with pliable ICs extends into flexible electronics including design of flexible circuits and integrating flexible assemblies into system manufacturing. Prior to American Semiconductor Mr. Chaney was employed at Micron Technology where he had responsibility for the Automotive, Industrial, Medical, and Military Segment for DRAM and NAND products. Mr. Chaney holds a BSEE from Texas A&M University, an MBA from San Jose State University and Multiple patents for data storage technology.
Shiuh-Kao Chiang, Prismark
Market and Technology Development of Advanced Packaging
kaoDr. Shiuh-Kao Chiang has a B.Sc. degree in Materials Science and Engineering from National Tsing Hua University in Taiwan, R.O.C., a M.S. degree in Metallurgical Engineering from University of Notre Dame, a Ph.D. in Ceramic Engineering from Ohio State University, and an Executive MBA degree from Cleveland State University.Shiuh-Kao's past experience includes material characterization, new product and process development, R&D management and technical marketing. Shiuh-Kao holds several patents, awards, and publications in electronic material, packaging, and processing areas. He joined Prismark in February 1998.Dr. Shiuh-Kao Chiang is responsible for the development of Prismark's business in Asia, as well as the management of research projects and services in Japan, Taiwan, China, Korea, Singapore, and other Asian countries. Over the past 15 years, Prismark has developed business and service relationships with most of the leading electronics, semiconductor, packaging, assembly, PCB and material companies in Asia. In addition, Prismark has also extended its services to leading financial institutions to assist their investments in Asia."
Frank D. Egitto, i3 Electronics
Miniaturization for Flexible and Flexible-Hybrid Electronics Applications
The wide range of applications for medical electronics drives unique requirements that can differ significantly from other electronics markets. This is particularly the case for handheld, portable, subcutaneous, in vivo, implantable, and wearable medical devices that demand increased functionality with decreasing size, weight, and power (SWaP). Form, fit, function, integrated sensors, batteries, leads, biocompatibility, operational life, and reliability specifications define requirements for atypical form factors, unique assemblies, and non-standard material sets. The medical industry is clearly and urgently in need of the development of advanced packaging that can meet the growing demand for miniaturization, high-speed performance, and flexibility. To accomplish this, new, smaller packaging structures need to be able to integrate more dies with greater function, higher I/O counts, smaller die pad pitches, and high reliability. Advanced microflex coupled with ultra fine flip chip assembly is well suited to meeting the challenge of extreme miniaturization and unique form factors requirements. This paper reviews several microflex applications for single-sided and double-sided flexible and flexible-hybrid applications.
Frank D. Egitto is Director of Research and Development at i3 Electronics, Inc. in Endicott, NY. His area's activities focus on materials, equipment, design, and process development for fabrication of high-density flexible circuitry, semiconductor packaging, and printed wiring boards. He holds B.A. and M.A. degrees in physics from Binghamton University and has over thirty-six years of experience working in the microelectronics industry. He is author or coauthor of 8 book chapters and over 80 technical papers, and holds 87 US patents.
Mike Ellsworth, IBM
Liquid (Water) Cooling Today's High Performance Computers
Early bipolar large system (mainframe) computers started out as air cooled systems cooled but soon evolved to be water cooled for a variety of reasons, mainly to cope with relatively high component heat fluxes and high overall system heat dissipation levels. The advent of and transformation to low powered CMOS chip technology in the early 1990's resulted in departure away from water cooling and back to the more traditional air cooling pervasively used to this day. Once again, particularly in the high performance or supercomputer space, water cooling is back on the scene, but is not implemented as it was before and not for the same reasons. We'll briefly revisit how and why water cooling was done in the past and then take a look at how and why water cooling is being done today with a brief glimpse as to how water cooling may be done in the future.
ellsworthMr. Ellsworth, a Senior Technical Staff Member with IBM in Poughkeepsie, NY, is currently the thermal lead for the water cooled pIH Supercomputing System and its follow-ons. He received his B.E.M.E. (1984) and M.E.M.E. (1988) from Manhattan College in Riverdale, NY. While at IBM he has explored improved thermal management for applications ranging from laptops to high-end servers and has investigated thermal technologies encompassing air, water, and refrigeration. He is a member of ASHRAE and IEEE, and is also a Fellow of ASME where he served on the Electronics and Photonics Packaging Division Executive Committee and on the K-16 Committee on Heat Transfer in Electronic Equipment. He has authored or co-authored more than 30 technical papers and is a co-inventor on nearly 170 US patents.
Amy Fleischer,Villanova
The Recovery and Reuse of Waste Heat in Data Centers
The capture and reuse of waste heat from a variety of industrial sources is gaining attention worldwide, but the low quality of data center heat makes the use of these recovery systems challenging for data center operators despite the large quantity of heat produced. Our research has focused on evaluating all available low grade waste heat recovery techniques, comparing their operational requirements with standard data center operating conditions, and evaluating their projected thermodynamic and economic performance. Our work identifies several potential avenues for successful waste heat recovery and reuse in data centers with significant economic potential.
fleischerDr. Amy Fleischer is a Professor of Mechanical Engineering at Villanova University where she is also Associate Chair of Mechanical Engineering and Director of Graduate Studies. She heads the NovaTherm Research Laboratory where her research interests include the broad topics of sustainable energy system design and thermal management of electronic systems. Recent research projects have included development of nano-enhanced materials, energy storage in phase change materials, and waste heat recovery from data centers. Dr. Fleischer is recognized as an expert in thermal-fluid system design and was elected by her peers as Chair of the ASME Technical Committee on Electronics Thermal Management (2009-2011). She has received numerous awards from her peers including the "2010 ASME EPPD Women Engineer of the Year Award" which recognizes a women engineer with significant technical achievements in the area of electronic and photonic packaging demonstrated through papers, patents, or product development. She was also the recipient of the 2011 ASME K-16 Clock Award for "Outstanding and continuing contributions to the science and engineering of heat transfer in electronics."Amy is an Associate Editor of the Journal of Heat transfer, a past AE of the Journal of Electronic Packaging, the author of numerous technical peer reviewed papers, and has edited one book. 
Sean Garner, Corning
Ultra-Slim Flexible Glass for Optical and Electronic Applications
As optical and electronic devices evolve to become lighter, thinner, and more flexible, the substrate choice continues to be critical to their overall optimization. The substrate directly affects improvements in the designs, materials, fabrication processes, and performance of advanced electronics. With their inherent benefits such as surface quality, optical transmission, hermeticity, and thermal and dimensional stability, glass substrates enable high-quality and long-life devices. As substrate thicknesses are reduced below 200um, ultra-slim flexible glass continues to provide these inherent benefits to high-performance flexible devices. In addition, the reduction in glass thickness also allows for new device designs and high-throughput, continuous manufacturing enabled by roll-to-roll processes. This paper provides an overview of flexible glass substrates and how they enable optical and electronic device optimization.
garnerSean Garner received a B.Eng. degree in Engineering Physics (Applied Laser and Optics) from Stevens Institute of Technology in 1993 and a Ph.D. in Electrical Engineering (electrophysics) from the University of Southern California in 1998. In 1998, Sean began his career at Corning Incorporated, working in the area of materials processing and device prototyping at the company's Science and Technology Center.
Charan Gurumurthy, Intel
Embedded Applications in Substrate Packaging
  This presentation reviews Intel's Embedded Array Capacitor (EAC) technology for high performance computing applications and embedded Wafter Level Packaging (eWLB) technology for mobile applications. EAC is a large array capacitor embedded in the core of high density interconnect (HDI) substrate. It provides a low inductance electrical path to the CPU. This presentation reviews the concept, benefits and challenges associated with EAC development. eWLB is a fan out die embedding packaging technology that involves reconstitution of silicon die into artificial wafer, multi layer fan out redistribution and ball out for interconnection using backend assembly. This presentation reviews the concept of eWLB along with its various advantages and applications.
  Charan Gurumurthy serves as Area Manager in Substrate Packaging Technology Development (SPTD), Intel Corp. His team's responsibilities include setting and executing to substrate packaging roadmap to meet Intel's product needs across all market segments. He manages the engineering activities across two substrate R&D fabrication facilities in Chandler, AZ. Charan joined Intel in 2002 from IBM Microelectronics Division, where he worked as a Senior Engineer in IBM's Assembly Process Development (APD) in Endicott, NY. Charan holds a Ph.D in Materials Science and Engineering from Cornell, MS in Industrial Engineering from SUNY Binghamton and BS in Mechanical Engineering from Indian Institute of Technology. Charan also currently serves as Associate Editor for IEEE's Transactions on Components, Packaging and Manufacturing Technology.
Alan Huffman, RTI
2.5D and 3D Technologies and Applications at RTI International
Advances in 2.5D and 3D integration technologies have ushered in a new era of microelectronics systems and are fundamentally changing how the industry looks at microsystems from consumer electronics to military system applications. While 2.5D and 3D integration is conceptually straightforward and generally well understood by most in the industry at this point, the implementation of these technologies to different devices and applications almost always requires the development of a custom solution. For that reason, flexible technologies and processes that can address a number of different requirements provide a "toolbox" of enabling capabilities that can be applied to a variety of applications and device types.For more than a decade, RTI International has been developing 2.5D and 3D process technologies and applying them to a number of demonstration test vehicles and functional device applications. Processes for forming functional TSV and TGV interconnects, high-density multilayer routing on devices and substrates, off chip interconnect through high-density bump interconnect arrays, wafer thinning and handling of thinned devices for front and backside wafer processing, and assembly techniques have been developed. This presentation details RTI International's process technology capabilities and demonstration vehicles and provides insight into how they can be tailored and applied to various applications.
huffmanAlan Huffman is a Research Engineer and Program Manager for wafer level packaging technologies with the Electronics and Applied Physics Division at RTI International. He received the Bachelor of Science in physics from the University of North Carolina - Chapel Hill in 1994 and joined the former MCNC - Research and Development Institute thereafter. From 1994 to 2005 he was a Member of the Technical Staff at MCNC-RDI working on the development and implementation of flip chip technologies, reliability and failure mode analysis of flip chip devices, and optoelectronic and MEMS packaging. In 2005 he joined RTI International after their acquisition of the MCNC-RDI research groups. His current work focuses on wafer level packaging technologies, characterization of polymers and other materials for WLP applications and 2.5D interposer and 3D integration technologies. He has authored or co-authored numerous papers, articles, and presentations on a number of advanced interconnect and packaging topics. Alan is a Senior Member of IEEE and a member of the IEEE CPMT and IMAPS societies.
Speaker: Subramanian S. Iyer, IBM
Abstract: When you can't scale the chip, start scaling the package and the Board
As conventional device scaling slows to a grinding halt driven primarily by increased development and manufacturing costs with saturating returns, computing is experiencing a paradigm shift characterized by highly associative and contextual environments, approximate or probabilistic computations and very adaptive or dynamic structures.
Interestingly, while silicon scaled by a factor of 1000 in the last four decades or so, most packaging and board metrics have scared far more modestly- at best a factor 4 or so. There are sound economic reasons for this lag but the future points to an era where packaging will provide very significant gains to systems scaling. Specifically, using memory as a paradigm, we will address the issue of scaling the package and the board as means to improve the cost-power-performance tradeoffs and argue that significant gains can be achieved through novel system integration constructs in spite of the saturation of "classical" silicon scaling.

iyerSubramanian S. Iyer is an IBM Fellow at the Systems & Technology Group, and directs the System Scaling Technology Function at IBM Microelectronics. He obtained his B.Tech. at IIT-Bombay, and Ph.D. at UCLA. His key technical contributions have been the development of the world's first SiGe base HBT, Salicide, electrical Fuses, embedded DRAM and 45nm technology used at IBM and IBM's development partners. He also was among the first to commercialize bonded SOI for CMOS applications through a start-up called SiBond LLC. He has published over 200 papers and holds over 65 patents. His current technical interests and work lie in the area of packaging and three-dimensional integration for system level scaling, as well as the long-term semiconductor and packaging roadmap for logic and memory. He is a Distinguished Alumnus of IIT Bombay and received the IEEE Daniel Noble Medal for emerging technologies in 2012. He also studies Sanskrit in his spare time.

Steve Ready,PARC
Printing of Multi-Functional 3D Objects
3D rapid prototyping equipment has progressed to the point that one can envision applications where high value customized products are additively printed into existence. PARC has been a leading innovator in this space with over a decade of experience in large area electronics, application of novel and current printing technology to industrial applications and the printing of electronic circuits and devices. We are currently applying this knowledge to the concept of printing multi-material 3 dimensional objects with electronic and/or mechanical functionality. The concept is to develop capability and provide means of manufacturing functional objects which may be difficult to manufacture or even not be manufacturable by other means. Our progress to date will be presented and future work will be discussed.
readySteve Ready obtained his degree in Physics from the University of California at Santa Cruz. He then joined Xerox Palo Alto Research Center and has since studied the role of hydrogen in amorphous, polycrystalline and crystalline silicon and has contributed to the development of large area amorphous and polycrystalline silicon imaging arrays for optical and x-ray applications. Recently he has designed and developed several high-accuracy inkjet printers for printed organic electronics and documents.
 Speaker: Bahgat Sammakia, Binghamton University
  bhagatDr. Bahgat Sammakia, a distinguished professor of mechanical engineering, is the vice president for research. A former IBM senior technical staff member, Sammakia joined Binghamton's faculty in 1998. He is the founding director of the Small Scale Systems Integration and Packaging Center, a New York State Center of Excellence, and is the director of the Energy-Smart Electronic Systems Center, a NSF I/UCRC founded in 2011 with a focus on reducing the energy consumed by data centers around the world. Sammakia earned his bachelor's degree from the University of Alexandria in Egypt and his master's and doctoral degrees from the University at Buffalo. He is a fellow of the American Society of Mechanical Engineers and a senior IEEE member. Sammakia, editor of the ASME Journal of Electronic Packaging, holds 14 U.S. patents and has published more than 180 peer-reviewed technical papers.
Harry, Schoeller, Universal
Effect of Sn Component Surface Finish on 92.5Pb-5Sn-2.5Ag
"92.5Pb-5Sn-2.5Ag solder, or a close variant, is widely used in high temperature electronics, such as down-hole and well-logging electronics, because of its high melting temperature (296°C) and superior fatigue resistance. However, selection of the right component surface finish is critical for solder joint performance. There are many options for component finish which not only change the composition of the interfacial intermetallic compound, but of the solder joint itself. One popular finish for high temperature electronics is matte Sn. During reflow, Sn, which has a much lower melting temperature (232°C) than 92.5Pb-5Sn-2.5Ag, dissolves into the solder changing the composition of the final joint. The final joint composition is a function of solder volume, Sn thickness, and wetting area.
This work investigates the effect of Sn component surface finish on the melting temperature, microstructure, and mechanical behavior of 92.5Pb-5Sn-2.5Ag. 92.5Pb-5Sn-2.5Ag was doped with up to 7% Sn to simulate the final composition of the joint after reflow. Differential Scanning Calorimetry (DSC) was used to measure the change in liquidus temperature with increasing Sn concentration. Microstructure and mechanical tests were carried out on 20 mil solder spheres reflowed on high temperature polyimide test coupons. Solder joints of each composition were cross-sectioned to examine the microstructure and interfacial reactions. The area fraction of β-Sn and Ag3Sn was quantified for each composition using image analysis software.
Shear and isothermal fatigue tests of individual solder joints with varying Sn concentrations were conducted at room temperature and 200°C. Joints were also sheared and fatigue tested at 200°C after aging for 1000hrs at 200°C to simulate a down-hole environment. After failure the fracture surfaces were examined to determine the mode of failure.
Beyond providing guidance for surface finish selection, this work examines the microstructure and mechanical behavior of 92.5Pb-5Sn-2.5Ag as a function of Sn concentration and temperature. An understanding the microstructure-mechanical performance relationship will aid in the development of new alloys for high temperature applications."
schoellerDr. Harry Schoeller (Ph.D., Materials Science and Engineering, Binghamton University, Binghamton, NY) is a Process Research Engineer at Universal Instruments Co. where he conducts research in the area of reliability of electronic packages. His research interests include high temperature electronics, mechanical properties of materials, microstructure analysis of metals, and thermal interface materials. Dr. Schoeller has published several refereed technical and conference articles on these subjects. He is a member of IMAPS, MRS, ASME and SMTA.
Dave Shaddock, GE Global Research
High Temperature Laminate Characterization
Printed circuit boards have been reported to have limited lifetime at 200 to 250C. Characterization and modeling high temperature laminates for application at 200 to 250C was conducted to better quantify the mean lifetime using accelerated testing of key functional parameters. Life testing and model development was applied for via cyclic life, peel strength, and weight loss. The high temperature laminates consisting of 3 types were evaluated. Via lifetime was characterization using Interconnect Stress Test (IST) coupons. Peel strength was tested using IPC IPC-TM-650 method 2.4.8c. Weight loss was characterized using isothermal and thermogravimetic analysis. Comparison of lifetime is made between the laminate samples.
shaddockDave Shaddock is an Electronics Packaging Engineer at the General Electric Global Research. He received a B.S.M.E. degree from Carnegie-Mellon University and M.S.Eng. Sci. in Microelectronics Manufacturing from Rensselear Polytechnic Institute. His research interests are in harsh environment electronics, thermal management, electronics manufacturing and reliability. He has 30 years of experience in electronics manufacturing and packaging at GE, Rockwell, and Motorola.
Aric Shorey, Corning
Through Glass Via Substrates: Technology, Performance and Applications
There has been substantial work done in the past few years to apply glass solutions for Advanced Packaging. Advantages of glass based solutions create significant opportunities by leveraging economies of scale, forming substrates at design thickness and leveraging thermal and electrical properties.
The ability to utilize both wafer and panel-based metallization strategies for filling glass vias has been shown. Transitioning these processes to cost-effectiveness and high throughput have shown great promise. The electrical performance of glass relative to silicon at high frequencies makes glass solutions very attractive, particularly in RF applications. Electrical models and characterization have demonstrated the advantages of the insulating properties of glass, and its positive impact on functional performance. Reliability tests show that glass solutions can meet device requirements. The progress and ability to exploit the properties of through glass vias to enable enhanced performance will be presented.
Glass based solutions in panel format provide exciting and cost effective industry opportunities by leveraging economies of scale and glass forming technology. Existing technologies can be used to fill glass vias in a panel format, as well as apply redistribution layers. We will present the status of leveraging panel based technology to enable cost effective glass interposers.
shoreyAric Shorey has been Commercial Technology Manager for the Semiconductor Glass Products program at Corning, Incorporated since 2011. He has BS/MS in Mechanical Engineering and a PhD in Materials Science – all from the University of Rochester. He has spent the majority of his career leading development activities in material's characterization, precision finishing and metrology for the telecommunications, precision optics and semiconductor industries.
Satish Kandlikar, RIT
Cooling Options for 3D-IC Cooling
3D IC architecture is seen as the next phase in improving performances of computer devices. The third dimension provides an opportunity for reducing the interconnect lengths with resultant performance improvements, cooling of these devices presents a new set of challenges. The conflicting requirements of interchip cooling and through silicon vias for data and signal transfer pose a unique set of challenges. The cooling options available for cooling these devices is briefly explored, and some of the work done in the area of high heat flux removal at the Thermal Analysis, Microfluidics and Fuel Cell Laboratory at Rochester Institute of Technology are discussed.
kandlikarSatish Kandlikar is a Gleason Professor of Mechanical Engineering at Rochester Institute of Technology. His areas of expertise include high flux electronics cooling, cold plates, fuel cells, pool and flow boiling and microchannel heat transfer and microfluidics. He has published over 350 journal and conference papers. He has received a number of awards including the ASME 2012 Heat Transfer Memorial Award.
Ning-Cheng Lee, Indium Corp
Abstract: Prospect of future interconnect materials for 2.5D and 3D packaging systems

Ning-Cheng Lee is the Vice President of Technology of Indium Corporation of America. He has been with Indium since 1986. Prior to joining Indium, he was with Morton Chemical and SCM. He has more than 20 years of experience in the development of fluxes and solder pastes for SMT industries. In addition, he also has very extensive experience in the development of underfills and adhesives. He received his PhD in polymer science from University of Akron in 1981, and BS in chemistry from National Taiwan University in 1973.Ning-Cheng is the author of "Reflow Soldering Processes and Troubleshooting: SMT, BGA, CSP, and Flip Chip Technologies" by Newnes, and co-author of "Electronics Manufacturing with Lead-Free, Halogen-Free, and Conductive-Adhesive Materials" by McGraw-Hill. He is also the author of book chapters for several lead-free soldering books. He received 1991 award from SMT Magazine and 1993 and 2001 awards from SMTA for best proceedings papers of SMI or SMTA international conferences, and 2008 award from IPC for Honorable Mention Paper – USA Award of APEX conference. He was honored as 2002 Member of Distinction from SMTA, 2003 Lead Free Co-Operation Award from Soldertec, 2006 Exceptional Technical Achievement Award from CPMT, 2007 Distinguished Lecturer from CPMT, 2009 Distinguished Author from SMTA, and 2010 Electronics Manufacturing Technology Award from CPMT. He served on the board of governors for CPMT, serves on the SMTA board of directors. Among other editorial responsibilities, he serves as editorial advisory board of Soldering and Surface Mount Technology, Global SMT & Packaging and as associate editor for IEEE Transactions on Electronics Packaging Manufacturing. He has numerous publications and frequently gives presentations, invited to seminars, keynote speeches and short courses worldwide on those subjects at international conferences and symposiums.

Kang-Wook Lee, Tohoku University
3D Hetero-Integration Technologies for Innovative Convergence Systems
Three-dimensional (3-D) hetero-integration technology allows the possibility of assembling various kinds of functional blocks such as processor, memory, sensors, logic, analog, photonics, and power ICs into one stacked chip. Therefore it can create innovative convergence systems beyond mobile and consumer products such as big data server, cloud computing system, smart energy harvesting system, radioactivity safety system, and future automotive integrated system. However, hetero-integration of different functional devices has many technical challenges owing to various types of size, thickness, and substrate of different functional devices, because they were fabricated by different technologies. In the symposium, I introduce a couple of innovative convergence systems as important potential applications and mainly address 3-D hetero-integration technologies developed by Tohoku University to realize such convergence systems.
wookKang-Wook Lee received the Ph.D. degree in machine intelligence and systems engineering (currently bioengineering and robotics) from Tohoku University, Sendai, Japan, in 2000. From 2000 to 2001, he was an engineer for Japan Science and Technology Corporation, Sendai, Japan. From 2001 to 2002, he was a postdoctoral researcher for Rensselaer Polytechnic Institute, Troy, New York, USA. From 2002 to 2008, he worked at Memory Division, Samsung Electronics Ltd., Korea, as a principal engineer. He joined to Tohoku University as a faculty in 2008 and currently with New Industry Creation Hatchery Center, Tohoku University, as a Professor. he has published more than 170 technical articles. He is a IEEE Senior Member.
Dr. Tao Li, University of Michigan
Sub-Millimeter Packages for Microsystems in Harsh Downhole Environments
The exploration and production of fossil fuels presents an important opportunity and need for sensing microsystems. Data on temperature, pressure and other variables in the wellbore, hydraulic fractures, and eventually in the reservoir, is valuable for maintaining quality, efficiency, and safety. Packaging of these microsystems plays an essential role in determining system applicability and performance in the harsh downhole environments, and accounts for a significant portion of device manufacturing cost. This presentation reviews the microsystem packaging technologies and the requirements on packaging in typical high temperature, high pressure and corrosive downhole environments. An example implementation of a sub-millimeter-scale package that can survive the harsh environments will be described, which is intended to encapsulate microsystem components including sensor chips, electronic chips and batteries. A chip integration strategy inside the package will be presented. Example test results of the packages in American Petroleum Institute standard brine will be discussed. A batch mode implementation of a low temperature packaging process for high throughput and low manufacturing cost is currently under investigation.
taoDr. Tao Li is an Assistant Research Scientist (research faculty member) in the Department of Electrical Engineering and Computer Science at the University of Michigan, Ann Arbor. He is also a faculty member with the Center for Wireless Integrated MicroSensing and Systems (WIMS2) at the University of Michigan. He received the B.S. and M.S. degrees in engineering from Tsinghua University, China, and Ph.D. in Electrical Engineering from the University of Michigan, Ann Arbor in 2009. His research interests include micromachined sensors and actuators, sensor interface and embedded systems, CMOS electronics, microsystem packaging, and traditional Si-based and nontraditional microfabrication technologies. He has about 30 journal and conference publications and 4 patents issued or pending.
Weiping Liu, Indium
Performance of Low Ag SACM0510 Solder Alloy for Mobile Electronics Applications
The drop shock resistance of solder joints in electronics is critical to the lifetime of mobile electronic products using ball grid array (BGA) and/or chip scale packages (CSP). The use of high Ag main stream SAC alloys has been challenged by the poor drop shock resistance of solder joints and the high cost of Ag. A low-Ag SAC alloy such as SAC105 was considered a solution for resolving both issues. However, this approach compromised the temperature cycling performance, and it is not acceptable for high end applications. Earlier a low Ag SAC alloy doped with Mn, SACM, has been reported with considerable improvement in shock resistance and thermal fatigue performance. In this study, within the family of SACM, a second generation alloy SACM0510 was developed with significantly more improvements. The reliability performance of the new SACM0510 solder alloy was evaluated in the form of BGA solder bump against SAC105 in JEDEC drop test, dynamic bending test, and IPC-9701 -55/125C temperature cycling test. The improvement in drop shock resistance essentially eliminates the need of underfilling for BGA and CSP on mobile devices. The SACM0510 alloy was also evaluated as solder paste for drop test and thermal aging performance. Results indicate the SACM0510 alloy is superior in the form of both BGA solder bump and solder pastes.
weipingDr. Weiping Liu is a research metallurgist for Indium Corporation. He received his Ph.D. in Materials Science and Engineering from the Harbin Institute of Technology, China, in 1989 and subsequently performed post-doctoral work at the Technical University of Berlin, Germany. Weiping was a professor at the Dalian Jiaotong University in China and a visiting scientist at the Max-Planck Institute for Metals Research in Stuttgart, Germany. He was also affiliated with the Joining and Welding Research Institute (JWRI) in Osaka University, Japan, and was part of the Materials Science and Engineering Department at Lehigh University, PA, USA. Dr. Liu's areas of expertise include materials joining, processing and alloy development. He has published about 80 research papers in these areas, and has received several "best paper" awards at international conferences. He also holds patents in alloys and processing. Dr. Liu was awarded the American Welding Society's Masubuchi Award in 2004 for "an outstanding scientist under the age of 40 who has made significant contributions in the advancement of the science and technology of materials joining through research and development", and the Robert L. Peaslee Memorial Brazing Award in 2013. He is a certified IPC Specialist for IPC-A-600 and IPC-A-610D, and has a Six-Sigma Green Belt from the Thayer School of Engineering at Dartmouth College. He was included in the Marquis Who's Who in America and Marquis Who's Who in Science. Dr. Liu also served on the International Scientific Advisory Board for the AWS and ASM organized International Brazing and Soldering             Conferences in 2000, 2006, and 2009.
Eric MacDonald, University of Texas - El Paso
3D Printing Multi-Functionality: Mechanical Structures with Electronics and Electromagnetics
Recently, research has concentrated on 3D printing for not only creating conceptual models but functional end-use products as well. By democratizing the manufacturing process, products will inevitably be fabricated locally with mass customization based on the specific requirements of the end user. However, 3D printing is generally limited to single material fabrication and consequently can only create mechanical devices with structural features such enclosures. For 3D printed end-use products to be profoundly significant, the fabrication technology will need provide fabricated structures with additional features in terms of electronic, electromechanical, electromagnetic, thermodynamic, optical, biological, chemical and pharmacological content. In the last decade, research has been reported of embedding electronic components and electrical interconnect into 3D printed structures either by interrupting the process or by inserting the additional content after the structure has been built. However, only until recently have fabricated devices with electromechanical properties been reported in which moving parts with control have been 3D printed with a 3D printing, non-assembly process. This paper describes the fabrication of an electromechanical device through 3D printing with enhanced electromagnetic function as well through 3D spatial control of material with permeability gradients. The device includes single piece construction of a coil and magnet motor with embedded electronic control. Although simple in conception, the ability to 3D print moving parts with electromechanical control will be seminal in terms of mass customized, 3D printed end-use products such as 3D printed UAVs, bio-implantable drug delivery systems or robotics.
mcdonaldEric MacDonald, Ph.D. is the Texas Instruments Endowed Professor in the Department of Electrical and Computer Engineering and associate director of the W. M. Keck Center for 3D Innovation at the University of Texas at El Paso. Dr. MacDonald received his B.S. (1992), M.S. (1997) and Ph.D. (2002) degree in Electrical Engineering from the University of Texas at Austin. He worked in industry for 12 years as a chip designer until 2002 working at IBM and Motorola. He co-founded a start-up - Pleiades Technologies, Inc. - specializing in self-test circuitry and CAD software. The company was acquired by Magma Inc. San Jose, CA. Dr. MacDonald joined UTEP in 2003 and has held faculty fellowships at NASA's Jet Propulsion Laboratory, the Office of Naval Research and a Fulbright Fellowship in Chile. His research interests include 3D printed electronics, ultra-low power chip design and electronics for harsh environments. Recent projects include 3D printing of structures like nano satellites with electronics in the structure (one of which was launched into Low Earth Orbit in late 2013 and a replica of which is on display at the London Museum of Science), bio-medical devices and 3D sensor systems. He has over 40 referred publications, three patents (one of which was licensed by Sony from IBM) and has taught over a thousand graduate and undergraduate engineering students.
Amy Marconnet, Purdue
Nanoengineering Materials for Heat Dissipation
Nanostructuring materials allows independent control of multiple materials properties. High conductivity materials such as carbon nanotube forests are useful as TIMs for dissipating power in electronic devices, while low conductivity materials like nanoporous silicon for thermal barrier coatings and enhanced thermoelectric performance. Beyond thermal transport, storage of thermal energy is critical for effective heat removal for applications involving highly-transient heat fluxes, such as during operation of multiple core processors. This talk will discuss:
  • Methods to push the thermal conductivity to the extremes by understanding and controlling the phonon transport at the nanoscale.
  • The development of a thermoreversible phase change material for efficient energy storage.
marconnetAmy Marconnet is an assistant professor of Mechanical Engineering at Purdue University. She received a B.S. in Mechanical Engineering from the University of Wisconsin – Madison in 2007, and an M.S. and a PhD in Mechanical Engineering at Stanford University in 2009 and 2012, respectively. She then worked briefly as a postdoctoral associate at the Massachusetts Institute of Technology, before joining the faculty at Purdue University in 2013. Research in the Marconnet Thermal and Energy Conversion Lab (M-TEC) integrates metrology and analysis of underlying transport mechanisms with design and development of nanostructured materials for heat transfer and energy conversion applications.
Patrick McCluskey, Associate Professor of Mechanical Engineering, University of Maryland
mccluskeyDr. Patrick McCluskey (Ph.D., Materials Science and Engineering, Lehigh University) is an Associate Professor of Mechanical Engineering at the University of Maryland, College Park, where he conducts research at the Center for Advanced Life Cycle Engineering (CALCE) in the areas of thermal management, reliability, and packaging of electronic systems for use in extreme temperature environments and high power applications. Dr. McCluskey has published more than 90 refereed technical articles on these subjects, and has edited three books. He has also served as technical chairman for multiple international conferences and workshops. He is an associate editor of the IEEE Transactions on Components, Packaging, and Manufacturing Technology, a fellow of the International Microelectronics and Packaging Society (IMAPS), and a member of ASME, IEEE, and SAE.
Hiroyuki Okabe, Shando
High Performance Flex Substrate for LED / Optical Transmission
As is shown in recent progress of wearable devices, data processor modules with high density circuits keep seeking chances to shrink themselves smaller than yesterdays.High performance flex like TAB/COF which is famous for fine pitch circuit, is now contributing the rapid evolution of such small form factor devices.On the other hand, flex is not well known for conductor of heat or light.Applying unique technologies of TAB/COF, LED substrates which can dissipate heat from a die to its mother board and optical substrate which can reflect light from optical fibers from/to tx/rx devices have been developed recently.The technologies and the results of evaluations on the substrates are mainly clarified in the presentation.
okabeHiroyuki Okabe is a deputy Director in Package Materials Production Division of Shindo Electronics, responsible for business development with TAB/COF related technologies.He joined Shindo in 2013 through the acquisition of the division from Hitachi Cable. He worked for over 25 years in the company where he mainly managed development and design engineering of TAB/COF applications and technologies.He received B.E. degree in Applied Chemistry from Waseda University (Japan) in 1987.
Speaker: Bob Patti, Tezzaron
2.5/3D Integration Technology and Applications
  As we reach the limits of shrinking transistors new frontiers are being explored and among them 2.5D and 3D integration of semiconductors is closest at hand and is already producing results. The presentation will discuss methods for producing the new vertical integration, technology readiness and applications.

Bob Patti is founder and CTO of Tezzaron Semiconductor Corporation BSEE/CS and BSPH, Rose-Hulman Institute of Technology, 1985.Area Minors: solid state electronic, applied optics, and Russian. Tezzaron specializes in high performance memory components, employing wafer level stacking of semiconductor sub-components. Prior to his affiliation with Tezzaron, Mr. Patti founded ASIC Designs, Inc. (ADI), of which he was the President and Chief Executive Officer from 1987 to 2000.Mr. Patti is actively provides system design and guidance to other members of the Tezzaron staff. Also, as time allows, he provides consulting services in the areas of design troubleshooting and yield enhancement. To date, Mr. Patti has been involved in the designing of over 100 ICs as well as numerous portable PCs, set-top boxes, and other high volume products.He is Member, Board of Directors, Tezzaron Semiconductor Corp, Scientific Advisory Board, Pharmaseq, Rose-Hulman Nano-Technology Advisory Board, IEEE Former Vice Chairman, JEDEC Future Memories (DDR III) Industry Award, SEMI Award for North America 2009 for Pioneer work in the emerging technical area of 3D IC integration.

William Polinsky, MS Kennedy
High Temperature Hybrid Microcircuit Challenges
MSK will discuss utilizing MCM's (multichip modules), also known as hybrid microcircuits, at temperatures above 125'C and up to 232'C. A general description of packaging challenges that MCM manufacturers face at elevated temperatures will be presented. Specific focus will be given to thick film printing of resistors on alumina and their characterization. MSK will present results of its actual high temperature life testing of MSK printed resistors as compared to discrete solutions.

William Polinsky has been with the MS Kennedy since 2007 and has served as High Temperature Product Line / Business Development Manager since February 2012 and Ceramics Group Product Line Manager from November 2007 until February 2012. From 1998 to 2007, Mr. Polinsky served Micron Technology in a variety of semiconductor fabrication and device packaging positions beginning with Process Engineer and ending with Engineering Manager. Mr. Polinsky holds a Bachelor of Science in Electrical Engineering from Rochester Institute of Technology, and a Master's in Business Administration from the Walden University.

Neil Poole, Henkel
Abstract: Novel Adhesives as a Means of Component Reinforcement for Hand Held Applications

With hand held devices becoming thinner and thinner the need to reinforce components against thermal cycle, shock, and flexing is likely to become more important. These changing demands must also be set against the need for reworkability to save increasingly expensive components. These competing requirements cannot simply be achieved by adjusting the CTE/Tg of existing products but requires new approaches to the problem both in the chemistry and in the application of the adhesive. Using this approach a variety of potential solutions have been generated from High Tg reworkable underfills to a range of partial underfills for less demanding applications.


Dr. Neil Poole is currently a Chemistry Fellow working in Henkle's Electronics Materials Technical Service group, working with customers on new product developments. Neil gained both his Bachelors and Doctorate from The University of Edinburgh, Scotland. After which he spent time working in the polymer and bulk chemicals industry before settling in electronic materials. He is the owner of multiple patents and has authored papers on such diverse topics as Heterogeneous catalysis, soldering, and underfills.

Alan Rae, Alfred Technology Resources
Defeating Counterfeit Electronics
Counterfeit goods widely available range from the trivial to the life threatening - from handbags to pacemakers, from olive oil to pharmaceuticals. This talk will review the "arms race" between counterfeiters and the rest of us trying to ensure that our customers receive a safe and effective product.
Dr. Rae has worked in the electronics, ceramics, nanotechnology and "clean tech" industries for over 25 years in the USA and UK, managing global businesses and technology development at a startup, operating company and corporate level. He is currently Executive Director of Alfred Technology Resources Inc. (ATRI), operating the Ceramics Corridor Innovation Centers in Alfred NY and Painted Post NY to stimulate economic development in the region. He is also holds positions with two ATRI subsidiaries, as CEO of the NanoMaterials Innovation Center in Alfred, NY and as President of ReNew Rare Earth Inc., a start-up business extracting rare earth materials from post-consumer electronics and industrial by-products.Alan is active in industry associations and standards work with iNEMI, ISO, IEC, SMTA, IMAPS, and IPC. He is a founder member of the Graphene Stakeholders' Association and was a member of the National Academies' Triennial Review of the NNI in 2012-2013 with a special focus on commercialization.
David Smukowski, Sensors in Motion
Success and Challenges of Size weight and Power (SWAP) Inertial system Development
Improving azimuth determination accuracy with small, lightweight, low power and cost technologies is not only the most effective means for solving GPS Denial for agriculture, military and drones, but will lead to improvement in Oil and Gas exploration and many other sensor systems. Sensors in Motion (SIM) has developed an 8 micro-electro-mechanical (MEMS) sensor system technology at its heart, but the biggest challenges have resided in both micro and macro packaging.
smukowskiDavid Smukowski is CEO of Sensors in Motion, a technology spin-out from the California Institute of Technology and NASA's Jet Propulsion Labs. SIM develops the best performing MeMs based sensors that represent a paradigm breakthrough in sensor technology.Prior to SIM, he was Managing Director of Boeing Ventures overseeing hundreds of business cases where he founded MessageGate, a message filtering company to manage e-mail content for corporate networks. He also created and was initial CEO of Exostar, the world's largest business to business ecommerce company. Collectively, he raised over $220M externally to fund ventures. He was President and Chief Operating Officer of Berkshire-Hathaway controlled FlightSafety Training International a global $500M company, taking it to 20% ROA. Before that, he spent 15 years as a Boeing executive for Business Strategy and Corporate Development. Highlights include the formation of its Services division (now 20% of revenues) and multi-billion dollar acquisitions and restructures. He was instrumental in developing lean initiatives, enterprise computing systems, core competencies and competitive strategies. Earlier he managed Boeing Energy and Environmental Affairs. He was an advisor to the White House and Department of Defense on Global Warming, Energy Conservation, Stratospheric Ozone Depletion and Waste Reclamation. His early years were spent in design and analysis of alternative energy, water management and aerospace structures. He co-founded Sustainable Seattle in 1990 and is active in a variety of academic and global issues of business sustainability and poorest of the poor solutions. Smukowski started with a degree in Civil and Environmental Engineering from the University of Wisconsin-Madison where he sits on its Board. He lectures and is a Board member of the University of Washington School Foster School of Business CIE, advises University of Pennsylvania - Wharton School and the University of Wisconsin on Corporate Innovation, Entrepreneurialism and Sustainability. He participates on multiple business, trade and civic boards. He was named U.S. Congress Employee of Excellence, honored by President George H. Bush (41) and Awarded University of Wisconsin Distinguished Achiever.
Speaker: Gerald Trant, GE

Gerald P. Trant joined GE Ocean Systems Division in 1978 at Syracuse, NY and has held various leadership positions including Signal Electronics Manager, Electronics and Software Sub-section Manager, and Signal, Power, Analog and ASICs Sub-Section Manager to design and produce Submarine (688i Los Angeles class and SSN21 Seawolf) and Surface Ship Combat Control Systems. He has held various Technical Leadership positions in Syracuse with then-GE division of Lockheed Martin Ocean & Radar Systems Division. In 1995, he was promoted to the New Products Introduction (NPI) Manager for GE Energy in Salem, VA for the design and production of the next-generation Turbine Control (Mark VI, EX2100, LCI Static Starter) and Drive products.
In 2002, Jerry was named Global Technology Manager, Micro and Nano Structures Technologies at GE Global Research, the advanced technology arm for GE. The 175 person, 10 laboratory global team is based in Niskayuna, New York. The team has been responsible various electronic & photonic devices and subsystems which include the Apollo Digital XRAY detector, LightSpeed VCT detector, MR coils, MEMS (Micro-Electro-Mechanical Systems), Microfluidics, Silicon Carbide Power Electronics, ASICs (Analog Application Specific Integrated Circuits), Harsh Environment Sensors and Solar PV.
A native of Westfield, MA, Jerry is a 1981 graduate of Syracuse University where he earned a Master of Science Degree in Engineering. He is a graduate of GE's Advanced Course in Engineering and the Edison Engineering Program.

Speaker: Christopher Williams, Virginia Tech
Embedded Actuation and Sensing Via Multi-Material 3D Printing and Direct Write
  When AM is combined with Direct Write of (DW) of conductive materials, the resulting hybrid process enables the direct manufacture of parts that feature embedded electronics, including interconnects and sensors. However, the hybridization of DW and AM technologies is non-trivial because of (i) identifying DW materials and processes that are compatible with AM infrastructure, throughput and resolution, (ii) temperature processing requirements, and (iii) interactions between the two materials.In this presentation, the authors discuss their efforts in hybridizing a DW system for depositing conductive materials into the PolyJet manufacturing process. The resulting system is able to create embedded and functional electronic interconnects and sensors in printed parts composed of both flexible and stiff polymers. In addition, the authors will present an approach for embedding shape memory alloys into printed parts to realize embedded actuating elements. When coupled with the ability to embed actuating elements (e.g., shape memory alloy wire), it is possible to directly fabricate "smart" mechatronic systems that feature actuated joints with integrated sensing.
  williamsChristopher B. Williams is an Associate Professor with a joint appointment with the Department of Mechanical Engineering and the Department of Engineering Education at Virginia Tech. He is the Director of the Design, Research, and Education for Additive Manufacturing Systems (DREAMS) Laboratory. His research contributions have been recognized by six Best Paper awards at international design, manufacturing, and engineering education conferences. He is a recipient of a National Science Foundation CAREER Award (2013), the 2012 International Outstanding Young Researcher in Freeform and Additive Fabrication Award, and the 2010 Emerald Engineering Additive Manufacturing Outstanding Doctoral Research Award. Chris holds a Ph.D. and M.S. in Mechanical Engineering from the Georgia Institute of Technology (Atlanta, Georgia) and a B.S. with High Honors in Mechanical Engineering from the University of Florida.
Chris Spadaccini, Lawrence Livermore National Lab
Additive Manufacturing and Architected Materials
Material properties are governed by the chemical composition and spatial arrangement of constituent elements at multiple length scales. This fundamentally limits material properties with respect to each other creating trade-offs when selecting materials for a specific application. For example, strength and density are inherently linked so that, in general, the more dense the material, the stronger it is in bulk form. We are combining advanced microstructural design, using flexure and screw theory as well as topology optimization, with new additive micro- and nanomanufacturing techniques to create new material systems with previously unachievable property combinations. We have demonstrated designer properties resulting from architected materials in polymers, metals, ceramics and combinations thereof. Our manufacturing techniques include Projection Microstereolithography (PuSL), Direct Ink Writing (DIW), and Electrophoretic Deposition (EPD). These tools are capable of generating the designed structures which are highly three-dimensional micro- and nano-scale architectures with multiple constituent materials in the same structure. Design of materials, fabrication, and characterization will all be discussed.
Dr. Christopher M. Spadaccini is currently the Principal Investigator of several advanced materials and additive manufacturing projects at the Lawrence Livermore National Laboratory (LLNL). He is also the founder and director of a new additive manufacturing and process development center at LLNL. The work in these laboratories focuses on developing next generation additive processes which are capable of micro- and nano-scale features and have the ability to create components with mixtures of materials ranging from polymers to metals and ceramics. Development of these processes also involves the synthesis and materials science of feedstocks such as photopolymers and nanoparticles. These capabilities are utilized to fabricate microarchitected materials with unique designer properties such as negative thermal expansion or ultra-light weight materials with high stiffness and strength. Dr. Spadaccini has been a member of the technical staff in the Materials Engineering Division at Lawrence Livermore National Laboratory for the past ten years. He received the S.B., S.M., and Ph.D. degrees from the Department of Aeronautics and Astronautics at the Massachusetts Institute of Technology (MIT) in 1997, 1999, and 2004 respectively. He has authored over four dozen journal and conference publications, three book chapters, and has multiple patents awarded. Dr. Spadaccini is also a part-time lecturer at the San Jose State University in the Biomedical, Chemical and Materials Engineering Department where he teaches graduate courses in advanced transport phenomena.
Chuck Woychik,Invensas Corporation
Advanced Interconnectology for Next Generation Mobile Devices
Consumer demands on today's mobile products continue to pose challenges associated with providing increased performance at reduced power and component size. Smartphone and tablet features such as high resolution video and multi-window operation will require increased data transfer rates while using less power in order to extend battery life; which has become a chief criteria amongst users. Considering that traditional packaging can no longer be considered independently from system design when addressing such challenges, the goal of "interconnectology" is to facilitate more rapid electronics product advancement through development of novel interconnect technologies. One such example is Invensas' "Bond-Via-Array" or "BVA" which provides a new high-density "Package-on-Package" (PoP) vertical interconnect technology for high-bandwidth memory-to-processor operation. BVA PoP offers more than 4-times the interconnect density of conventional PoP while leveraging existing fine-pitch wire bonding assembly capability. The result is a significantly advanced component that can be readily manufactured for upcoming mobile products.
Charles Woychik is Senior Director of 3D Technology for Invensas Corporation™, a San Jose based leader in semiconductor packaging and 3DIC technology []. He currently has been with the company for 4 years. Prior to Invensas, Chuck worked 5 years for General Electric Global Research, after spending the first 18 years of his career with IBM. His area of expertise is materials and processes for electronics packaging. He holds a doctorate and Masters of Science degree in Materials Science and Engineering from Carnegie-Mellon University. He has a Bachelor's of Science degree in Materials Science from the University of Wisconsin, Madison. Chuck has numerous publications and 54 issued US patents to his credit.
Tomoyuki Yamada, Kyocera
Next Generation Organic Substrate Technologies; Low CTE Organic Interposer and Embedded components.
In recent years, a 2.5D package has been developed to accommodate high-speed data processing and miniaturization in microelectronics. In the industry, most of the development work has been implemented with silicon interposer technology, which was fabricated with legacy wafer manufacturing equipment. This is because of the excellent ground rules available for silicon and the lower Coefficient of Thermal Expansion (CTE) when compared to organic substrate technology.
The body size for 2.5D packages has been increasing, which is driven by the number of logic and memory chips per interposer as well as their footprints. Due to the body size limitation of silicon interposers, there is a significant industry need for a large organic interposer to support high-performance 2.5D packages.
This presentation describes the development of a low-CTE organic Chip Scale Package (CSP) for 2.5D packaging. The new material set, identified as ""Advanced SLC Package"", combines a low-CTE core with build-up dielectric materials to achieve a composite laminate CTE of around 11 ppm/C, which is between that of silicon devices and conventional PCBs.
The composite CTE reduces the dimensional mismatch between chip and laminate during Bond and Assembly (BA) to mitigate Chip-Package Interactions (CPI). The low CTE significantly reduces the strain in the solder joints during the reflow process and ensures solder joint reliability. In addition, the CTE mismatch of device solder interconnect pads between the silicon chip and laminate during device attach is less pronounced during the C4 joint cooling-down period. In this presentation, the design rules will be examined based upon the new low-CTE organic material parameters as well as the CSP form factor. This presentation will also highlight organic substrate technology with embedded Passives/Actives.
yamandaTomoyuki Yamada was graduated from Osaka University in Japan in 1997 and holds the master degree of material science.In 1997, he joined IBM japan as process engineer for organic substrate. In 2003, the division was acquired by Kyocera SLC technology corporation and he assumed engineering manager position. Currently, he is a Sr Field Applications Engineer as well as development engineer to develop next generation organic substrate technology in Fishkill, NY"
Binghamton University State University of New York
PO BOX 6000   Binghamton, NY 13902-6000

Last Updated: 10/4/14