Our 33rd Annual Electronics Packaging will be held in-person this year. Please check the main page for the speaker and session chair info.
On this page, we would like to share with you the speakers and session chairs who will participate in our 33rd Annual Electronics Packaging Symposium. This page will fill up with speakers and session chairs as they are confirmed.
Session Chairs and Speakers
Session 0: Keynotes - Benson Chan (Binghamton), Nancy Stoffel (GE)
Speaker: Xin Wu (AMD), 08:30AM – 09:10AM, September 7th
Title: Integrated Circuits, Hetero-Integrations and Inter-discipline Engineering
Along with the slowing down of the Moore’s Law, more and more semiconductor integrated circuits (ICs) depend on hetero-integrations to further advance in power, performance and cost reduction. Unlike in previous years, hetero-integrations require far more close inter-laced joint efforts between many engineer disciplines, such as electrical, mechanical, material sciences, thermal as well as optical engineering, in order to become successful.The semiconductor industry will only further move following this trend in the future.Therefore, broadening knowledges, both in the school education as well as in continual learning while during work, would provide more opportunities for engineers to become more successful in today and in future semiconductor IC industry.
Speaker: Frank Gayle (NIST), 09:10AM – 09:50AM, September 7th
Title: NIST, Semiconductors, and the CHIPS & Science Act
With the CHIPS and Science Act signed into law in August 2022, the nation has a unique opportunity to bolster the U.S. integrated circuit and packaging production supply chain. Furthermore, with $11 billion in appropriated funds for both research and development, and education and workforce development, we can prepare for long-term U.S. leadership in microelectronics. This talk will present the opportunities described in the legislation and the approach that NIST and the Department of Commerce are taking for implementation. In addition, the capabilities of the NIST research labs in metrology and standards support of the microelectronics industry will be described.
Session 1: Heterogeneous Integration – William Chen (ASE Fellow and Senior Technical Advisor)
Speaker: Robert Patti (Nhanced Semi), 10:10AM - 10:40AM, September 7th
Title: 2.5/3D Heterogeneous Integration
Moore’s Law predicted the sustained scaling that our industry has enjoyed for decades. End consumers have come to expect ever-increasing functionality at lower cost with each passing year. However, in the coming decade the limits of physics will forcibly slow the pace of geometric scaling, perhaps all but ending it. In the face of this issue, the industry is looking for new ways to fulfill the end consumer’s expectations. 3D integrated circuits have emerged as the best near-term solution to mitigate the roll-off of geometric semiconductor scaling. The power of 3D circuit integration lies in its ability to intimately integrate diverse materials and processes as well as reduce wire length. The ramifications of this are more far-reaching than one might initially realize. 3D wiring changes alone might provide a 5-30% device improvement, but new combinations of disparate circuit types and new 3D optimized architectures make 100-500% improvements possible.
Speaker: Hemanth Dhavaleswarapu (AMD), 10:40AM - 11:10AM, September 7th
Title: Advanced Packaging: Enabling Heterogeneous Integration through Chiplet Architectures
Advanced packaging enabled chiplet architectures are increasingly adopted to drive performance and cost improvements. This talk describes novel packaging architectures being enabled by AMD, direct Cu-Cu bonding technology used in AMD’s 3D VCache architecture and its comparison to the industry standard 3D architectures. The challenges facing the chiplet integration will be discussed in detail with particular focus on thermals and mechanics. Other technologies that are being enabled to advance high performance computing architectures will also be previewed.
Speaker: Alan Huffman (Skywaters), 11:10AM - 11:40AM, September 7th
Title: Don’t Forget the Package: Establishing Domestic Heterogeneous Integration Capability
The recent passage of the CHIPS legislation has initiated a new era of semiconductor technology growth in the United States, with the goal of re-establishing advanced domestic microelectronics manufacturing to support both commercial and government applications.While much of the focus in the re-shoring discussion has been on leading edge foundry capability, heterogeneous integration (HI) and advanced packaging (AP) technologies are critically important in establishing a complete ecosystem to support domestic microelectronics.As HI architectures are viewed as crucial enablers for next generation microsystems to maintain performance improvements that are difficult and costly to achieve through foundry node advancement, establishing these technologies onshore will be a priority.This presentation will discuss details around this unique opportunity to establish a comprehensive domestic integration and packaging manufacturing capability and SkyWater’s efforts to establish an open foundry model to support interposer fabrication, FOWLP, and hybrid bonding technologies.
Session 2: Future of Computing for HPC/AI – Sathya Raghavan (IBM), Aakrati Jain (IBM)
Speaker: Arvind Kumar (IBM), 01:00PM - 01:30PM, September 7th
Title: Heterogeneous Integration for the Future of AI
The explosive growth of AI is accompanied by ever-increasing demands of compute, memory, and bandwidth. Meeting these demands sustainably while logic scaling provides diminishing benefits is well-aligned with the heterogeneous integration paradigm.
In this talk I will discuss the opportunities for heterogeneous integration to meet the challenging demands of AI, examining both the architecture requirements as well as the packaging technologies needed to enable an upward trajectory for system performance.
Speaker: James Sexton (IBM), 01:30PM - 02:00PM, September 7th
Title: Future Computing Challenges and Opportunities
This is a particularly disruptive time for the development of future computing systems, and the next 10 years will see some very fundamental shifts in how those systems are architected and deployed. With the emergence of AI and Quantum, we are seeing an explosive growth in computational techniques be supported on future computing systems and in computing solutions to support those techniques. At their heart, the challenges and opportunities systems architects now face are founded in silicon technology. In this talk we will present those opportunities and challenges, and we’ll offer thoughts on the implications for future chip design and development.
Speaker: Hemanth Jagannathan (IBM), 02:00PM – 02:30PM, September 7th
Title: Foresights on CMOS technology scaling to 2nm and beyond
What are the prospects for the future of CMOS logic technology? Have we hit the scaling brick wall? What is beyond FinFETs? Is 2nm technology realistic? Are there any realistic technologies beyond 2nm? With the many questions and uncertainties, we face for the future of CMOS technology, there are also endless possibilities for innovation and research. This talk will review the tremendous advancements in CMOS technology over the past decades. It will also address the challenges that CMOS technology scaling faces today and provide an outlook for the future of computational technology scaling while diving into the challenges and opportunities that lie ahead of us.
Session 3: Thermal Challenges, Automotive and Harsh – Ramchandra Kotecha (GE)
Speaker: Gamal Refai-Ahmed (AMD), 10:10AM - 10:40AM, September 7th
Title: Roadmap and Challenges on the Next Generation of Thermal Interface Material for High Warpage Heterogeneous Package
With the constant increases of power density in silicon year after year, there is a constant strive to provide better thermal management innovation to improve thermal design solutions for the high-power density. The Thermal Interface Material (TIM) is a first-order solution for thermal management of high-power density silicon. This TIM plays a crucial role in defining the solution, both thermally and mechanically. This study addresses the challenges of the next generation of thermal Interface material for high warpage heterogonous package.
There is no question that Thermal Interface Materials (TIMs) materials have been helpful in coupling the IC packages thermally and mechanically to the thermal management solution and have addressed the issue of thermal contact optimally by displacing the air that is present between the irregular surfaces of the silicon and the heat spreader at the micro-level thereby decreasing the thermal contact resistance It also bridges the CTE (coefficient of thermal expansion) gap between two dissimilar materials.
This work points out challenges that the TIM material has to overcome to maintain its thermal performance without degradation over time which depends on its intrinsic characteristics defined by the elongation, adhesion, thermal conductivity, and bond line thickness (BLT). As the power density and the sizes of the packages increase when these are surface mounted on the board, they exhibit warpage during its operation. The die side of the package can be warped by 10% to 30% in the operating range of 50°C to 100°C as compared to the warpage of standalone silicon die at 20°C, which was observed by analyzing a baseline FCBGA package using Digital Image Correlation (DIC) approach. This warpage also created the need for the higher BLT of the TIM to cover the entire die surface, and this will also induce high stresses and may also cause TIM delamination during the lifetime of the device. Hence there is a surface interaction between the die and the TIM that occurs due to the thermal and mechanical behavior of the package, which dictates the device lifetime and performance degradation.
This study is given the roadmap of the first level of system-level interaction with the next generation of packages. Also, it reports the new finding on the impact of warpage and adhesion on the thermal interface resistance.
Speaker: Gilbert Moreno (NREL), 10:40AM – 11:10AM, September 7th
Title: Automotive Power Electronics Cooling Technology Research at NREL
The presentation will describe NREL’s automotive power electronics thermal management research activities. A brief description of existing automotive thermal management systems will first be provided. Advanced thermal management concepts developed at NREL will then be presented. Various advanced cooling concepts that use jet impingement and/or dielectric fluids (single and two-phase) will be described and their performance is compared to existing, on-road technology.
Speaker: Emad Andarawaris (GE), 11:10AM – 11:40AM, September 7th
Title: Recent Advances in High Temperature Electronics for Extreme Environments
Wide ranging applications including down-hole geothermal, turbine engines, high speed vehicles and space/planetary exploration have continued to demand increasing levels of sensing and controls in environments that often experience operating temperatures exceeding 300°C. Addressing these unique needs require novel device, packaging and reliability assessment approaches.
GE has developed and fabricated state-of-the-art wide bandgap electronics, such as silicon carbide (SiC) Metal Oxide Silicon Field Effect Transistor (MOSFETS). These electronics have been utilized to realize and demonstrate analog signal conditioning circuits operating up to 600°C. Recent testing has demonstrated long-term operation of a SiC CMOS inverter circuit held at 500°C thereby establishing a foundation for the implementation of scalable digital electronics for harsh environment operation.
The realization of extreme temperature electronics system is critical to achieving the sensing, control, and actuation goals of today’s most challenging thermal environments. This talk will cover our recent advances in extreme temperature electronics and packaging, and will address technology challenges, performance gaps that still remain, ongoing and future work towards addressing these gaps.
Session 4: Flexible and Additive Electronics – Mohammed Alhendi (Binghamton)
Speaker: Christine Kallmayer (Fraunhofer IZM), 01:00PM - 01:30PM, September 7th
Title: Materials and Technologies for Stretchable Electronics
3D conformable electronic systems have attracted considerable attention for several years. By using different technology approaches and materials, repeated stretchability as well as conformability of such systems have been shown by different research groups.
New technologies to realize such 3D electronics not only save weight and volume in already known applications. They also allow completely new functionalities and systemic changes in which structures and surfaces enable a novel interaction with the environment and human beings through integrated sensors, actuators and electronics.
Looking at the applications the different requirements become obvious: medical band aids or bandages are more or less strongly deformed depending on the position on the body and are subjected to dynamic repeated stretching loads. If a patch or textile bandage is equipped with electronic sensors which are to have close contact (no slipping or lifting) with the skin underneath, the electronic system must be able to follow the occurring curvature and elongation. A completely different situation exists when, for example, operating elements such as switches or sliders in the form of capacitive sensors are to be integrated into a 3D surface like the dashboard of a car.
The requirements for electronic systems, which have been outlined in the examples, can only partially be fulfilled with rigid and flexible circuit carriers. For the above-described novel application profiles and the technical requirements derived from them, stretchable and conformable electronic modules are required. The manufacturing and / or product concepts comprise electronic systems on polymeric or textile circuit carriers, which can be stretched one or more times by significantly more than 5%, thus enabling a smooth covering of three-dimensional free-form surfaces.
Stretchable and conformable Electronics that are largely based on established two-dimensional process technologies for the realization of the circuit carriers (printed circuit boards) as well as for the assembly will allow a smoother transfer to industry. The modules are manufactured in the same way as conventional electronic systems and do not develop their properties beyond the rigid and flexible printed circuit board before the last manufacturing step (thermoforming, molding) or in the application (eg as a soft electronic plaster).
Speaker: Deepak Trivedi (GE), 01:30PM - 02:00PM, September 7th
Title: Industrial Inspection Robotics – Opportunities for Flexible and Stretchable Electronics
In this presentation, I will discuss how soft robotics can take flexible and stretchable electronics to practically unreachable places, and enable inspection and repair of high-value industrial assets such as jet engines, aircraft and nuclear reactors without the need for expensive disassembly. The significant strategic and commercial advantages of in-situ industrial, military, and consumer inspection is driving the need for technological solutions beyond the fundamental limits of traditional robotics and electronics. In this talk, I will discuss (1) the unique constraints and challenges of in-situ industrial inspection robotics, and (2) how the confluence of soft mechanics and stretchable and flexible hybrid electronics are coming together to address these challenges. I will conclude with a perspective for future needs, challenges, and possibilities in the area of soft robotics for inspection of high-value industrial assets.
Speaker: Arvind Rangaran (HP Labs), 02:00PM - 02:30PM, September 7th
Title: 3D Printed Electronics with Multi Jet Fusion for Flexible Hybrid Electronics
The focus of this talk will be on 3D Printed Electronics (3DPE) with Multi Jet Fusion (MJF), a research-level activity led out of HP Labs. We will demonstrate the capabilities of MJF 3DPE towards Flexible Hybrid Electronics (FHE) applications. MJF 3DPE can take advantage of the voxel-scale control of conductive properties to print traces, vias, and pads anywhere within a parts 3D geometry. This enables construction of a 3D geometry that conforms to the shape and function intended by the designer. This accomplishes the goal of traditional FHE to create an electronic device on a flexible substrate, which is capable of being conformed onto a simple 3D geometry. Post-fabrication Pick and Place (P&P) will be demonstrated to attach components and create parts enabling the desired FHE functionality. Post-Processes techniques like aerosol jet printing (AJP) will also be highlighted to demonstrate conductive features with finer resolutions that of the MJF 3DPE process. This can create required feature scales not currently addressable by MJF 3D PE. We will also leverage advanced process control Digital Twin technology by appropriately collecting process and part data to enhance part and trace quality, predictability, and consistency of manufacturing output.
Session 5: mmWave and 5G/6G Packaging – Joe Iannotti (GE, Senior Principal Engineer)
Speaker: Shelby Nelson (Mosaic Microsystems), 08:00AM - 08:30AM, September 8th
Title: Thin Glass Interposers for mm-Wave Packaging Applications
Thin glass interposers with fine-pitch through-glass via (TGV) technology provide an advantaged solution for millimeter-Wave packages and systems integration. Electrical and physical properties of glass have attractive attributes such as low RF loss, thermal expansion coefficient matched to silicon in some cases, and low roughness with excellent flatness to achieve fine L/S. A hurdle to adopting glass as a packaging substrate has been the handling of large, thin glass substrates in standard automation and processing equipment. To leap that hurdle, we describe a temporary bonding technology that allows the thin glass substrates to be processed without the need to modify existing equipment, and which prevents breakage. In this talk, we will demonstrate the use of thin bonded wafers to create reference standards for characterization of dielectric properties. We also demonstrate the use of the temporary bond to fabricate void-free through-glass-via fill, for vias with aspect ratios from 2:1 to 8:1, in a bottoms-up process like that used for through silicon vias. We also provide examples where glass-based devices provide low loss, high-Q solutions for 5G/6G filters, low loss/high gain antennas for mm-Wave frequencies, and hermetic packaging for MEMS and sensors.
Speaker: Tom Rovere (Lockheed Martin), 08:30AM - 09:00AM, September 8th
Title: Additive Manufacturing for Heterogeneous Integration – Benefits and Challenges
Broad overview of the potential benefits of additive manufacturing with respect to heterogeneous integration as well as challenges associated with this transformative technology. Presentation will highlight some potential use cases.
Speaker: Craig Armiento (UMass - Lowell), 09:00AM - 09:30AM, September 8th
Title: Advances in Printed Microwave Systems: Materials and Devices
The realization of printed microwave systems requires advances in materials, printing technologies and design methodologies. This talk will review projects underway at the University of Massachusetts Lowell that address some of the challenges in exploiting additive technologies to fabricate microwave devices and subsystems. This talk will review ongoing efforts to develop new inks including low-loss dielectrics, high-Dk ferroelectric inks and insulator-to-conductor convertible inks. Research on bare die integration, additive packaging approaches and printed microwave connectors will also be discussed.
Session 6: Advance Substrates – Dishit Parekh (Intel)
Speaker: Vern Stygar (AGC), 10:00AM - 10:30AM, September 8th
Title: The Evolution of Technology and the use of Glass
This presentation will review some of the applications, packaging architecture, the various formulations of glass for these applications.
It has been a mere 60 years since the laser was invented by Bell labs. At that time, scientist claimed that a real-life application was not evident. Sixty years later the entire basis of our internet depends on lasers transmitting large volumes of data. What is the point? In any new technology there is an incubation period before the next generation of engineers and materials mature before to see the applications.
On this premise, the world is now pivoting to design packages that will incorporate devices that hybridize frequencies greater than 10 GHz with photonic devices. These devices have feature sizes scaled down to micron level and in some cases nano level. DNA sequencing and diagnostics applications are one good example.
Glass has not changed much since its discovery some 3,600 years ago. Basic compositions are alkali and non-alkali containing formulations. So, what makes glass uniquely suitable to the next generation of devices. Chemical and thermal stability, surface roughness approaching 0.5 nm and relatively low electrical loss. The choice of glass formulations, for semiconductor devices, is dependent upon process and final design. Properties such as warp, TTV, Light transmission, thickness, and dielectric constant need to consider in utilizing glass in a package. Moreover, glass is such a stable subtrate, specialize surface nano features can be etched into the glass.
Why glass. What has changed? The upper limit of the EUV reticle size (photomask) has been reached. The industry is now exploring 2.5 d packaging which integrate multiple functions on separate dies (chiplets) and then integrating these functions on single substrate: Heterogeneous Packaging. Couple with the increase density: I/O’s predicted to go from 10 vias per square mm to 10,000 vias per square mm in the next 10 years. Semiconductor products operating at frequencies in mm wave require extreme precision of lines and spaces. In addition, total thickness variation has to be under two microns. In those cases where vias are require, via diameter and positional accuracy require a tolerance of less than five microns.
Speaker: Kyu-oh Lee (Intel) (V), 10:30AM - 11:00AM, September 8th
Title: Advanced Substrate Roadmap for Heterogenous Integration
Advanced packaging technologies have been revolutionizing semiconductor manufacturing. Heterogeneous Integration (HI) has been playing a pivotal role in the advanced packaging to continue and complement the progression of Moore’s Law scaling through integration of separately manufactured components into a higher level assembly that provides enhanced functionality with lower total cost ownership and faster time to market. The industry has been developing a number of new and advanced packaging technologies to enable HI. Power, performance, area, and cost (PPAC) have been the key metrics for the adoption of HI technologies. This presentation will address key technology drivers and building blocks of the advanced substrate technology for heterogeneous integration by focusing on increased bandwidth, higher speed, lower latency, and lower power.
Speaker: Rajesh Vaddi (Corning), 11:00AM - 11:30AM, September 8th
Title: Innovative Solutions for microLED Displays
Emerging microLED displays continue to demonstrate progress toward display performance improvements that include: higher dynamic range, higher brightness, wider color gamut, and borderless designs. These potential advantages are being pursued for applications such as large area tiled displays smartwatches, and automotive displays. With these advantages, though, challenges to mass production exist related to the unique assembly and integration for microLED displays. Using large-area tiled displays as an example, this talk will outline engineered substrate and electrical interconnect solutions to address the microLED transfer assembly and tiled display integration challenges. This includes precision edged glass substrates with integrated metallized vias for backplane control.
Session 7: Wearable and Flexible Electronics – Mark Poliks (Binghamton University, SUNY Distinguished Professor of Engineering, Director, Center of Advanced Microelectronics Manufacturing- CAMM)
Speaker: Robert Shephered (Cornell), 08:00AM - 08:30AM, September 8th
Title: Tactile Perception in Robots via Stretchable Photonics
Speaker: Joey Mead (UMass Lowell - AFFOA), 08:30AM - 09:00AM, September 8th
Title: Stretchable Electronic Materials: Substrates, Conductive Textiles, and Encapsulants
The number of applications for stretchable materials and electronics is increasing, requiring new materials and processes to meet these requirements. Typical stretch requirements are often less than 50%, but future goals could increase these requirements and elastomer materials (both thermosets and thermoplastic elastomers) are seeing increased use. New textiles with embedded and printed electronics are also of interest. This talk will cover recent developments in materials for flexible and stretchable electronics such as substrates, conductors, encapsulants, and textile based materials. New substrates include tunable polymer-based substrates combining barium strontium titanate (BST) with both a thermoplastic and a thermoset elastomer. With variation in the filler loading, the dielectric properties of the material can be tailored and BST also generates a tunable substrate. The elastomer provides loadings of up to 40 vol % BST with high stretch good recovery (low permanent set). Substrates can be printed with a commercially available stretchable ink, providing a material with stretch over 100%. For soft robotics applications, textiles coated with an impermeable membrane and printed with a conductive ink can create a new sensor platform. Multiple designed strain sensor patterns can be transferred onto pre-prepared actuator surface via screen-printing method using stretchable and conductive silver ink (ACI materials SE1108). Two approaches were compared: one was to directly screen-print the pattern on rubber-coated fabrics, the second was to screen-print the pattern on a TPU membrane and then hot-compress the TPU membrane with the printed pattern onto fabrics. Braided carbon nanotube yarns in an elastomer matrix give unique structures with resistivity that is independent on the degree of stretch. Thus, these structures could be used for wires and connections in soft robotics or other applications. Superhydrophobic systems can be used as encapsulants that can be coated onto flexible and stretchable substrates. With the interest in smaller line dimensions, the patterning of the surfaces into regions of different wettability at the micro and nanoscale to give tailored wetting and compatibility with inks can be considered, along with scale up to roll to roll printing. The testing and evaluation capabilities for stretchable electronic materials at UML will also be described.
Speaker: Azar Alizadeh (GE), 09:00AM - 09:30AM, September 8th
Title: Fabrication of Multi-sensor Vital Sign Patches for Ambulatory Care
Wireless wearable devices can continuously assess and communicate the condition of patients and are crucial components of digital mobile health platforms. General societal trends across the globe, including a shortage of centralized laboratory and medical facilities, aging populations with increasing incidence of infectious and chronic diseases, earlier diagnosis of diseases, personalized medicine, companion testing for pharmaceutical use, government initiatives and insurance acceptance, are all important factors behind the demand for reliable, low-cost, wireless, wearable health monitoring devices. Fortunately, technological building blocks for implementation of these devices have evolved to the point that we believe that such monitoring will progress into a fully mobile approach in the near future, enabling continuous monitoring across acute, ambulatory and home care. In the past decade, a number of wireless physiological monitoring devices have been developed and tested in various clinical settings and a few of them are at early stages of product release. Furthermore, in 2020, due to the unprecedented circumstances of the COVID-19 pandemic, numerous wearable devices were investigated for early infection detection and patient monitoring in hospital and nursing home settings. In spite of this tremendous potential and significant investments by both device developers and government agencies, broad adoption of wearable medical devices has not yet been fully realized. The barriers to broad adoption include device cost and performance challenges, ease of use, integration of devices within the remote care flow system as well as lack of robust reimbursement models. In this paper, we will discuss flexible hybrid electronic manufacturing opportunities and challenges to create low cost, high performance wireless sensor systems for vital signs monitoring. We will highlight the critical need and progress towards enabling the supply chain workflows that allow for sustainable manufacturing solutions at large volumes.
Session 8: Power Electronics – Ramchandra Kotecha (GE)
Speaker: Satish Prabhakaran (GE), 10:00AM - 10:30AM, September 8th
Title: Silicon Carbide Integration for Megawatt-scale Aircraft Propulsion Systems
GE Aerospace and the U.S. National Aeronautics and Space Administration (NASA) have launched a hybrid electric technology demonstrator program as part of NASA’s Electric Powertrain Flight Demonstration (EPFD) project. Plans are to conduct ground and flight tests of a megawatt class hybrid electric propulsion system by the mid-2020s. GE, NASA, and partners will accelerate the introduction of hybrid electric flight technologies for commercial aviation.
Hybrid electric propulsion technologies that save fuel and optimize engine performance are key to GE’s commitment to help develop a more sustainable future of flight. This talk will cover aspects of silicon carbide -based component development, system integration and maturation towards a range of electric propulsion systems under development.
Speaker: Doug Hopkins (NC State), 10:30AM - 11:00AM, September 8th
Title: Heterogenous Integration of Power Electronics and the Road Ahead
Heterogenous Integration in power electronics has been occurring for many years at a macro scale. However, the need for microelectronics to continue past Moore’s law has resulted in major efforts to understand the complexities of integrating a larger plethora of heterogenous parts, and with it, a spill-over of process and thinking applied to power. This talk reviews the structure and projected outcome in the IEEE-EPS Heterogeneous Integration Roadmap – Chapter 10, addressing Integrated Power Electronics (IPE). The map covers the breadth of power integrated adjacent and within the data chips, as standalone power (e.g. board-mount power), as wearable and harvested, and at higher power such as in electric vehicles. There is substantial synergy in the approaches, but substantial divergency in the supply chain from parts to manufacturers. Every attendee will identify with some part of the map and technologies that are proposed.
Speaker: Stefan Behrendt (Danfoss Silicon Power), 11:00AM - 11:30AM, September 8th
Title: Inorganic Encapsulated Power Modules with Newly Implemented Thermal Paths
The ever-increasing requirements in terms of power density and reliability of power electronic modules make packaging an ever-increasing challenge. Polymers, which are primarily used today for the encapsulation of such modules, do not offer any thermal conductivity to effectively dissipate power losses (heat) from the modules. Inorganic encapsulation materials offer a promising approach to this problem. The materials used in this study have thermal conductivities of up to 3,8 W/m*K while maintaining the ability to be applied by a simple potting process. Through thermal simulations the influence of an elevated thermal conductivity is evaluated. Furthermore, these results form the base for two new module concepts which are designed to utilize the enhanced thermal conductivities of inorganic materials. Rth,ja could be reduced by up to 29% within the experiments.